公开(公告)号：WO2003036493A1

公开(公告)日：2003-05-01

申请号：PCT/US2002/030632

申请日：2002-09-26

Applicant: CHAPARRAL NETWORK STORAGE, INC.

Inventor： PECONE, Victor, Key

IPC: G06F15/16

CPC classification number: G06F13/385

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is connected to a passive backplane, and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module (104, 108), which communicates with the channel interface module (136, 140) via passive backplane (116), and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and two channel interface modules are used. The controller memory modules may mirror data between one another using the passive backplane and a shared communication path on the channel interface modules, thereby substantially avoiding the use of host or disk channels to mirror data.

Abstract translation: 公开了一种用于在主计算机和存储设备之间传送数据的网络存储控制器，例如廉价磁盘RAID的冗余阵列。 网络存储控制器包括至少一个与无源底板连接的通道接口模块，并且在主计算机和存储设备与无源底板之间选择性地传输数据。 网络存储控制器还包括至少一个控制器存储器模块104,108，该控制器存储器模块104,108经由无源底板116与信道接口模块136,140进行通信，并处理并临时存储从主计算机或存储设备接收的数据。 在需要冗余的应用中，至少使用两个控制器存储器模块和两个通道接口模块。 控制器存储器模块可以使用无源背板彼此之间的数据和通道接口模块上的共享通信路径进行镜像，从而基本避免使用主机或磁盘通道来镜像数据。

公开(公告)号：WO2003036484A1

公开(公告)日：2003-05-01

申请号：PCT/US2002/030631

申请日：2002-09-26

Applicant: CHAPARRAL NETWORK STORAGE INC.

Inventor： PECONE, Victor, Key

IPC: G06F13/00

CPC classification number: G06F11/2092 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2097

Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The channel interface module is connected to a passive backplane (112), and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module (104), attached to the passive backplane. The controller memory module communicates with the channel interface module via the passive backplane, and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required at least two controller memory modules and at least two channel interface modules are used. The controller memory modules may mirror data between one onother using the passive backplane and a shared communication path on the channel interface modules, thereby substantially avoiding the use of host or disk channels to mirror data. The channel interface modules are operable to selectively connect the host computer or storage device to one or more controller memory modules. The controller memory modules may include a DMA engine (188) to facilitate the transfer of mirrored data.

Abstract translation: 公开了一种用于在主计算机和诸如廉价磁盘（RAID）的冗余阵列等存储设备之间传送数据的网络存储控制器。 网络存储控制器包括至少一个通道接口模块，其适于连接到主计算机和存储设备。 通道接口模块连接到无源底板（112），并且在主计算机与存储设备和无源背板之间选择性地传送数据。 网络存储控制器还包括附接到无源底板的至少一个控制器存储器模块（104）。 控制器存储器模块经由无源底板与通道接口模块通信，并处理并临时存储从主机或存储设备接收的数据。 在需要冗余的应用中，使用至少两个控制器存储器模块和至少两个通道接口模块。 控制器存储器模块可以在使用无源底板的另一个之间的镜像数据和通道接口模块上的共享通信路径之间镜像数据，从而基本上避免使用主机或磁盘通道来镜像数据。 通道接口模块可操作以选择性地将主计算机或存储设备连接到一个或多个控制器存储器模块。 控制器存储器模块可以包括DMA引擎（188），以便于镜像数据的传送。

公开(公告)号：WO2003043254A3

公开(公告)日：2003-05-22

申请号：PCT/US2002/035786

申请日：2002-11-07

Applicant: CHAPARRAL NETWORK STORAGE, INC. ,  MAINE, Gene

Inventor： MAINE, Gene

IPC: G06F13/14

Abstract: A direct memory access (DMA) engine (70) has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor (78) associated with the primary controller. This command causes the DMA engine to access processor memory (74) to obtain medtdata therfrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory (82) and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

公开(公告)号：WO03043254A2

公开(公告)日：2003-05-22

申请号：PCT/US0235786

申请日：2002-11-07

Applicant: CHAPARRAL NETWORK STORAGE INC ,  MAINE GENE

Inventor： MAINE GENE

IPC: G06F13/28 ,  H04L

CPC classification number: G06F13/28

Abstract: A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain medtdata therfrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

Abstract translation: 直接存储器访问（DMA）引擎几乎与数据传输有关的所有控制可以涉及主控制器和辅助控制器之一或两者。 DMA引擎从与主控制器相关联的处理器接收与数据传输相关的命令。 该命令使DMA引擎访问处理器内存以获得其中的数据。 在执行DMA操作时，元数据允许DMA引擎在本地存储器和远程存储器之间进行数据传输。 在执行异或操作时，DMA引擎涉及使用本地存储进行数据传输。

公开(公告)号：WO2002093376A1

公开(公告)日：2002-11-21

申请号：PCT/US2002/015796

申请日：2002-05-17

Applicant: CHAPARRAL NETWORK STORAGE INC.

Inventor： DAVIES, Ian, R.

IPC: G06F11/00

CPC classification number: G06F3/0659 ,  G06F3/0605 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0683 ,  G06F11/2089

Abstract: The methodology of the present invention (100) automatically selects an unused id for a system component in a system where multiple other components with other ids are already present. In this manner, id conflicts are avoided.

Abstract translation: 本发明的方法（100）自动选择系统组件中的未使用的ID，其中已经存在其他id的多个其他组件。 以这种方式，可以避免id冲突。

公开(公告)号：WO2002071230A1

公开(公告)日：2002-09-12

申请号：PCT/US2002/006563

申请日：2002-03-04

Applicant: CHAPARRAL NETWORK STORAGE INC.

Inventor： BUSSER, Richard, W.

IPC: G06F12/08

CPC classification number: G06F11/1076 ,  G06F2211/1009 ,  G06F2211/1059

Abstract: A method for enhancing the performance on non-full stripe writes while closing the RAID5 write hole is disclosed. When a RAID controller receives data to be written to a disk array, the controller stores the data in nonvolatile memory, and opens a write operation. When the current write operation is initiated, the controller reads the old data from the disk array and checks for cached parity that corresponds to the stripe of data that is to be modified. If the parity is cached, the controller reads the cached parity, and if the parity is not cached the controller reads the old parity from the disk array. New parity is then computed. If the parity was cached, the controller will modify a parity log to show an outstanding data write. If the parity was not cached, the controller will open a parity log to show an outstanding data and parity write. The new parity is then cached in non-volatile memory. The controller then determines whether the following write operation is for the same stripe of data. If the following write operation is for the same stripe, the controller writes the new data to disk and opens a parity log for the following write operation to show an outstanding parity write, and terminates the current write operation. If the following write operation is not for the same stripe, the controller writes both the new data and new parity to disk, and terminates the current write operation.

Abstract translation: 公开了一种在关闭RAID5写入孔时提高非全条纹写入性能的方法。 当RAID控制器接收要写入磁盘阵列的数据时，控制器将数据存储在非易失性存储器中，并打开写入操作。 当启动当前的写入操作时，控制器从磁盘阵列中读取旧数据，并检查对应于要修改的数据条带的缓存奇偶校验。 如果奇偶校验被缓存，则控制器读取缓存的奇偶校验，并且如果奇偶校验未缓存，则控制器从磁盘阵列读取旧的奇偶校验。 然后计算新的奇偶校验。 如果奇偶校验被缓存，控制器将修改奇偶校验日志以显示未完成的数据写入。 如果奇偶校验没有缓存，控制器将打开一个奇偶校验日志以显示未完成的数据和奇偶校验写。 新的奇偶校验然后缓存在非易失性存储器中。 然后，控制器确定以下写入操作是否用于相同的数据条带。 如果以下写入操作是针对相同的条带，则控制器将新数据写入磁盘，并为下一次写入操作打开一个奇偶校验日志，以显示未完成的奇偶校验写入，并终止当前的写入操作。 如果以下写操作不是相同的条带，则控制器将新数据和新奇偶校验写入磁盘，并终止当前的写操作。

公开(公告)号：AU2002361603A1

公开(公告)日：2003-05-26

申请号：AU2002361603

申请日：2002-11-07

Applicant: CHAPARRAL NETWORK STORAGE INC

Inventor： MAINE GENE

IPC: G06F13/28 ,  G06F13/14

Abstract: A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain metadata therefrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

公开(公告)号：AU2002340679A1

公开(公告)日：2002-11-18

申请号：AU2002340679

申请日：2002-05-01

Applicant: CHAPARRAL NETWORK STORAGE INC

Inventor： BUSSER RICHARD W

IPC: G06F20060101 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F12/16 ,  G11C29/00 ,  H03M13/00

Abstract: A system and method for efficient parity mirroring between controllers of an active-active controller pair in a redundant array of inexpensive disks (RAID) system is disclosed. When a second controller in an active-active controller pair receives new data to be written to a disk array, it mirrors the new data to a first controller in the active-active controller pair. The second controller then computes new parity for the data stripe associated with the new data. The second controller then opens a parity log and mirrors logical block address (LBA) information for the new data to a first controller in the active-active controller pair. In the event of a failure of the second controller after mirroring the LBA information and prior to completing the write operation, the first controller uses the LBA information to complete the write operation, assuring that the new data and new parity are properly stored on the disk array. If a hard disk in the disk array fails, parity is mirrored between the first and second controllers, rather than just LBA information. If a hard disk and the second controller fail when the first controller contains LBA information, a list containing the LBAs is created and a media error is returned in the event that a host requests in the form of a read operation data contained in the listed LBAs.

公开(公告)号：GB2396463B

公开(公告)日：2006-04-12

申请号：GB0406740

申请日：2002-09-26

Applicant: CHAPARRAL NETWORK STORAGE INC ,  DOT HILL SYSTEMS CORP

Inventor： PECONE VICTOR KEY

IPC: G06F11/16 ,  G06F13/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/167

公开(公告)号：GB2396463A

公开(公告)日：2004-06-23

申请号：GB0406740

申请日：2002-09-26

Applicant: CHAPARRAL NETWORK STORAGE INC

Inventor： PECONE VICTOR KEY

IPC: G06F13/10 ,  G06F3/06 ,  G06F13/28 ,  G06F15/167

Abstract: A network storage controller (30) for transferring data between a host computer (50) and a storage device (54), such as a redundant array of inexpensive disks (RAID), is disclosed. The network storage controller includes at least one channel interface module (42) which is adapted to be connected to the host computer and storage device. The channel interface module (42) is connected to a passive backplane (38), and selectively transfers data between the host computer and storage device and the passive backplane. The network storage controller also includes at least one controller memory module, attached to the passive backplane (38). The controller memory module communicates with the channel interface module via the passive backplane (38), and processes and temporarily stores data received from the host computer or storage device. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used. The controller memory modules may mirror data between one another using the passive backplane and a shared communication path on the channel interface modules, thereby substantially avoiding the use of host or disk channels to mirror data. The channel interface modules are operable to selectively connect the host computer or storage device to one or more controller memory modules. The controller memory modules may include a DMA engine to facilitate the transfer of mirrored data.