公开(公告)号：WO03043254A9

公开(公告)日：2004-05-06

申请号：PCT/US0235786

申请日：2002-11-07

Applicant: CHAPARRAL NETWORK STORAGE INC ,  MAINE GENE

Inventor： MAINE GENE

IPC: G06F13/28 ,  G06F13/14

CPC classification number: G06F13/28

Abstract: A direct memory access (DMA) engine (70) has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor (78) associated with the primary controller. This command causes the DMA engine to access processor memory (74) to obtain medtdata therfrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory (82) and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

Abstract translation: 直接存储器访问（DMA）引擎（70）几乎具有与可涉及主控制器和辅助控制器中的一个或两者的数据传输相关的所有控制。 DMA引擎从与主控制器相关联的处理器（78）接收与数据传输相关的命令。 该命令使得DMA引擎访问处理器存储器（74）以获得其中的数据。 在执行DMA操作时，元数据允许DMA引擎在本地存储器（82）和远程存储器之间进行数据传输。 在执行异或操作时，DMA引擎涉及使用本地存储进行数据传输。

公开(公告)号：WO03043254A2

公开(公告)日：2003-05-22

申请号：PCT/US0235786

申请日：2002-11-07

Applicant: CHAPARRAL NETWORK STORAGE INC ,  MAINE GENE

Inventor： MAINE GENE

IPC: G06F13/28 ,  H04L

CPC classification number: G06F13/28

Abstract: A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain medtdata therfrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

Abstract translation: 直接存储器访问（DMA）引擎几乎与数据传输有关的所有控制可以涉及主控制器和辅助控制器之一或两者。 DMA引擎从与主控制器相关联的处理器接收与数据传输相关的命令。 该命令使DMA引擎访问处理器内存以获得其中的数据。 在执行DMA操作时，元数据允许DMA引擎在本地存储器和远程存储器之间进行数据传输。 在执行异或操作时，DMA引擎涉及使用本地存储进行数据传输。

公开(公告)号：AU2002361603A1

公开(公告)日：2003-05-26

申请号：AU2002361603

申请日：2002-11-07

Applicant: CHAPARRAL NETWORK STORAGE INC

Inventor： MAINE GENE

IPC: G06F13/28 ,  G06F13/14

Abstract: A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain metadata therefrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

公开(公告)号：WO2007047438A3

公开(公告)日：2009-04-30

申请号：PCT/US2006040093

申请日：2006-10-11

Applicant: DOT HILL SYSTEMS CORP ,  ASHMORE PAUL ANDREW ,  MAINE GENE

Inventor： ASHMORE PAUL ANDREW ,  MAINE GENE

IPC: G06F12/00

CPC classification number: G06F11/2069 ,  G06F11/2066 ,  G06F11/2079

Abstract: A data storage system configured for efficient mirroring of data between paired redundant controllers is provided. More particularly, in response to the receipt of customer data from a host for storage, a first controller segments the received customer data into one or more frames of data. In addition, the first controller determines or associates certain metadata for each frame of customer data, and inserts that metadata in the corresponding frame. The frames, including the metadata, are provided to a secondary controller. The secondary controller stores the customer data from a received frame in memory, and stores the corresponding metadata in another location of memory that is indexed to the location where the customer data was stored. The secondary controller may also associate a count value with each frame of data in order to distinguish the most recent frame of data should frames in memory have matching metadata.

Abstract translation: 提供了配置用于在配对的冗余控制器之间有效地镜像数据的数据存储系统。 更具体地，响应于从主机接收客户数据进行存储，第一控制器将所接收的客户数据分成一个或多个数据帧。 另外，第一控制器确定或关联客户数据的每一帧的某些元数据，并将该元数据插入到对应的帧中。 包括元数据的帧被提供给次级控制器。 次级控制器将来自接收到的帧的客户数据存储在存储器中，并将相应的元数据存储在索引到存储客户数据的位置的存储器的另一位置中。 次级控制器还可以将计数值与每个数据帧相关联，以便区分存储器中的帧的最新帧数据具有匹配的元数据。

公开(公告)号：WO2007002219A3

公开(公告)日：2007-03-29

申请号：PCT/US2006024179

申请日：2006-06-20

Applicant: DOT HILL SYSTEMS CORP ,  ASHMORE PAUL ANDREW ,  DAVIES IAN ROBERT ,  MAINE GENE ,  VEDDER REX WELDON

Inventor： ASHMORE PAUL ANDREW ,  DAVIES IAN ROBERT ,  MAINE GENE ,  VEDDER REX WELDON

IPC: G06F13/42 ,  G06F11/20

CPC classification number: G06F13/4269 ,  G06F11/2071 ,  G06F11/2074 ,  G06F11/2089

Abstract: A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a PCI-Express memory write request TLP to the second bus bridge. The TLP header includes an indication of whether the first CPU requests a certification that certifies the payload data has been written to the second write cache memory. If the indication requests the certification, the second bus bridge automatically transmits the certification to the first bus bridge independent of the second CPU, after writing the payload data to the second write cache memory. The first bus bridge generates an interrupt to the first CPU in response to receiving the certification. The certified transfer may be used to validate and/or invalidate mirrored copies of a write cache directory on the RAID controllers, among other uses.

Abstract translation: 公开了一种用于执行高效镜像张贴写入操作的系统，该系统具有经由PCI-Express链路进行通信的第一和第二RAID控制器。 第一个总线桥将PCI-Express存储器写请求TLP传输到第二个总线桥。 TLP报头包括第一CPU是否请求证明有效载荷数据已被写入第二写入高速缓冲存储器的证明的指示。 如果该指示请求认证，则在将有效载荷数据写入第二写入高速缓存存储器之后，第二总线桥接器自动将认证发送到独立于第二CPU的第一总线桥。 响应于接收认证，第一总线桥向第一CPU产生中断。 经过认证的传输可用于验证和/或使RAID控制器上的写入缓存目录的镜像副本无效，以及其他用途。

公开(公告)号：WO2004074996A3

公开(公告)日：2004-12-29

申请号：PCT/US2004004098

申请日：2004-02-12

Applicant: CHAPPARAL NETWORK STORAGE INC ,  MAINE GENE

Inventor： MAINE GENE

IPC: G06F20060101 ,  G06F3/06 ,  G06F11/20 ,  G06F13/36 ,  G06F15/16

CPC classification number: G06F11/2087 ,  G06F3/0601 ,  G06F2003/0692 ,  H04L67/1097

Abstract: A bus bridge apparatus for performing broadcasted writes to redundant memory subsystems in a network storage controller is disclosed. The bus bridge includes a PCI-X target that receives a write command on a first PCI-X bus on one side of the bridge. The target is coupled to two PCI-X masters coupled to primary and secondary memory subsystems by respective PCI-X buses on the other side of the bridge. A first FIFO buffers the write command data between the target and the first master, and a second FIFO buffers a copy of the data between the target and the second master. The first and second masters concurrently retransmit the write command on their respective PCI-X buses to the primary and secondary memory subsystems. However, the second master only retransmits if broadcasting is enabled and the write command address is in a broadcast address range known by the bus bridge.