公开(公告)号：EP0793343B1

公开(公告)日：2001-07-18

申请号：EP96830089.7

申请日：1996-02-29

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Pulvirenti, Francesco

IPC: H03K17/082

CPC classification number: H03K17/0822

公开(公告)号：EP0655711B1

公开(公告)日：2000-03-29

申请号：EP93830483.9

申请日：1993-11-30

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Mancuso,Massimo c/o SGS-THOMSONMICROELECTRONICS ,  Poluzzi, Rinaldo ,  Rizzotto, Gianguido

IPC: G06T5/00

CPC classification number: G06T5/002 ,  G06T5/20 ,  G06T2207/10016 ,  H03H2222/02

公开(公告)号：EP0881669A1

公开(公告)日：1998-12-02

申请号：EP97830259.4

申请日：1997-05-30

Applicant: STMicroelectronics S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Lombardo, Salvatore ,  Pinto, Angelo ,  Nicotra, Maria Concetta

IPC: H01L21/331

CPC classification number: H01L29/66242 ,  H01L21/26506

Abstract: A process for fabricating a vertical structure high carrier mobility transistor on a substrate (1) of crystalline silicon doped with impurities of the N type, having a collector region (2) located at a lower portion of the substrate, the process comprising the steps of:

defining a window (10) in the semiconductor substrate (1);
providing a first implantation of germanium (Ge) atoms through said window (10);
providing a second implantation of acceptor dopants through said window (10) to define a base region;
applying an RTA treatment, or treatment in an oven, to reconstruct the crystal lattice within the semiconductor substrate comprising a silicon/germanium alloy (Si 1-x Ge x );
forming a first thin dielectric layer (12) of silicon dioxide (SiO 2 ) by chemical vapor deposition; depositing a second dielectric layer (14) onto said first dielectric layer (12);
depositing a polysilicon layer (15) onto said second dielectric layer (14);
etching away, within the window region (10), said first (12) and second (14) dielectric layers, and the polysilicon layer (15), to expose the base region (3) and form isolation spacers (50) at the window edges;
forming an N-doped emitter (4) in the base (3) and window regions.

This fabrication process is specially attentive to the formation of the silicon dioxide SiO 2 /Ge x Si 1-x interface present in vertical structure HBT transistors, if isolation spacers are to be formed.
The fabrication process of this invention allows the frequency field of application of HBT transistors to be further extended, while eliminating deviations of the base currents from the ideal.

Abstract translation: 一种用于在掺杂有N型杂质的晶体硅的衬底（1）上制造垂直结构的高载流子迁移率晶体管的方法，其具有位于衬底下部的集电极区域（2），该方法包括以下步骤： ：在所述半导体衬底（1）中限定窗口（10）; 提供通过所述窗口（10）的锗（Ge）原子的第一注入; 提供通过所述窗口（10）的受体掺杂剂的第二注入以限定基极区域; 在烘箱中进行RTA处理或处理以重构包括硅/锗合金（Si1-xGex）的半导体衬底内的晶格; 通过化学气相沉积形成二氧化硅（SiO 2）的第一薄介电层（12）; 将第二介电层（14）沉积到所述第一介电层（12）上; 将多晶硅层（15）沉积到所述第二介电层（14）上; 在窗口区域（10），所述第一（12）和第二（14）电介质层和多晶硅层（15）之间蚀刻掉，以暴露基部区域（3）并在窗口处形成隔离间隔物（50） 边缘; 在基底（3）和窗口区域中形成N掺杂发射体（4）。 如果要形成隔离间隔物，则该制造工艺特别注意垂直结构HBT晶体管中存在的二氧化硅SiO 2 / G x Si 1-x界面的形成。 本发明的制造方法允许HBT晶体管的应用频率域进一步扩展，同时消除基极电流与理想电流的偏差。

公开(公告)号：EP0629001B1

公开(公告)日：1998-07-29

申请号：EP93830255.1

申请日：1993-06-10

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Palara, Sergio

IPC: H01L27/07 ,  H01L29/72

CPC classification number: H01L29/7802 ,  H01L27/0716 ,  H01L29/0878

Abstract: An integrated structure is described, that comprises a vertical bipolar transistor and a vertical MOSFET transistor, where, in order to reduce the series resistance of the MOSFET transistor, the collector region of the bipolar transistor and the drain region of the MOSFET transistor are both parts of a common zone and are contiguous each other, so that the high charge injection in the collector region when the bipolar transistor is in conduction state, causes a simultaneous increase in the conductivity of the drain region of the MOSFET transistor. Both transistors are formed by cells each containing an elementary bipolar transistor and an elementary MOSFET transistor.

公开(公告)号：EP0740491A1

公开(公告)日：1996-10-30

申请号：EP95830167.3

申请日：1995-04-28

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Aiello, Natale ,  La Barbera, Atanasio ,  Palara, Sergio

IPC: H05B41/00 ,  H02H5/04 ,  H03K17/08 ,  H05B41/29

CPC classification number: H05B41/2856 ,  H02H5/044 ,  H03K17/08126 ,  H03K2017/0806

Abstract: A monolithically integrated power device for driving electrical loads comprises a power stage (1) including a high-voltage bipolar transistor (TR1) and a low-voltage auxiliary transistor (M or TR2) cascade-connected and inserted between a first power supply terminal (C) and a second power supply terminal (S) of the device. The power device also comprises a driver circuit (4) for the power stage (1) having an input connected to an input terminal (IN) of the device.
In accordance with the present invention the device includes a circuit (3) for protection thereof against an excessive temperature rise and controlling power down of the power stage (1). It comprises specifically a temperature sensing circuit (5) which generates a signal dependent on the temperature present in the device, a comparator circuit (6) which receives this signal and compares it with a reference voltage (VREF) and at least a first switch circuit (I1) generating an interdiction signal when the temperature in the device exceeds a preset maximum value and which is interlocked with an output of the comparator circuit and connected functionally through its output to the power stage.
The device is advantageously usable e.g. in a fluorescent lamp driving circuit, that is to say the so-called "lamp ballast".

Abstract translation: 用于驱动电气负载单片集成功率器件包括一个高压双极型晶体管（TR1）和低压辅助晶体管（M或TR2）一个功率级（1）级联连接和第一电源端之间插入（ C）和所述装置的第二电源端子（S）。 功率器件，以便包括用于具有到连接到该装置的输入端（IN）上的输入功率级（1）的驱动电路（4）。 在与本发明雅舞蹈的装置包括用于保护其对抗在过度的温度上升，并控制功率的功率级（1）的向下的电路（3）。 它专门包括一个温度检测电路（5），该基因率的信号依赖于存在于所述装置中的温度，一个比较器电路（6），其接收该信号并将它与一个参考电压（VREF）和至少一个第一开关电路比较 （I1）在遮断信号产生时该装置中的温度超过预设最大值和所有其互锁在比较器电路的输出，并通过其输出到功率级功能性地连接。 该装置有利地是可使用的E.G. 在荧光灯驱动电路，确实就是所谓的“灯镇流器”。

公开(公告)号：EP0730299A1

公开(公告)日：1996-09-04

申请号：EP95830066.7

申请日：1995-02-28

Applicant: CO.RI.M.ME.

Inventor： Aiello, Natale

IPC: H01L27/02

CPC classification number: H01L27/0248

Abstract: A circuit (30) for biasing epitaxial wells of a semiconductor integrated circuit comprises a first transistor (T1) and a second transistor (T2) driven in phase opposition to the first; when the supply voltage is positive, the first transistor (T1), being connected between the power supply and the epitaxial well, is conducting whereas the second transistor (T2) is cut off. When, on the contrary, the supply voltage is negative, the second transistor (T2), being connected between the epitaxial well and the ground reference GND, goes into saturation, thereby holding the epitaxial well biased to ground since, at that time, it is the highest potential present on the device. In this way, it becomes possible to always ensure reverse biasing of the parasitic diodes which form at the junctions between the epitaxial wells and the adjacent regions thereto.

Abstract translation: 用于偏置半导体集成电路的外延阱的电路（30）包括与第一晶体管相位相反地驱动的第一晶体管（T1）和第二晶体管（T2） 当电源电压为正时，连接在电源和外延阱之间的第一晶体管（T1）导通，而第二晶体管（T2）被切断。 相反，当电源电压为负时，连接在外延阱和接地参考GND之间的第二晶体管（T2）进入饱和状态，从而保持外延良好地偏置于地，因为在那时 是设备上存在的最大潜力。 以这种方式，可以始终确保在外延阱和其相邻区域之间的结处形成的寄生二极管的反向偏置。

公开(公告)号：EP0608667B1

公开(公告)日：1996-08-21

申请号：EP93830034.0

申请日：1993-01-29

Applicant: SGS-THOMSON MICROELECTRONICS S.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: H03K17/687

CPC classification number: H03K17/0414 ,  H03K17/04123 ,  H03K17/687

公开(公告)号：EP0713163A1

公开(公告)日：1996-05-22

申请号：EP94830535.4

申请日：1994-11-17

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO ,  SGS-THOMSON MICROELECTRONICS S.r.l.

Inventor： Colletti, Paolo ,  Bontempo, Gregorio ,  Pulvirenti, Francesco ,  Gariboldi, Roberto

IPC: G05F1/573

CPC classification number: G05F1/573

Abstract: The purpose of the present invention is to supply a method and a circuit simple and accurate enough to protect at least one transistor against exceeding a complex limit implying processing of multiple electrical quantities associated with said transistor.
Since in many practical cases said complex limit corresponds to the product of at least two quantities, typically a current and a voltage, the circuit in accordance with the present invention generates electrical signals basically proportional to said quantities, multiplies them, compares the product with a reference signal corresponding to the limit placed on the transistor and acts on the transistor in such a way that said limit is not exceeded.
Advantageously the multiplication of currents can be provided simply by means of connection in series of bipolar transistor junctions at which said currents are supplied to the respective emitters. In this case it is additionally advantageous to generate the reference signal by means of connection in series of the bipolar transistor junctions in such a manner as to have an analogous behaviour of the multiplier and the generator.

Abstract translation: 本发明的目的是提供足够简单且准确的方法和电路，以保护至少一个晶体管免受超过复数限制，这意味着与所述晶体管相关联的多个电量的处理。 由于在许多实际情况下，所述复数极限对应于至少两个量（通常为电流和电压）的乘积，所以根据本发明的电路产生与所述量基本成比例的电信号，将其乘以它们，将产品与 参考信号对应于放置在晶体管上的极限，并以不超过所述极限的方式作用在晶体管上。 有利地，电流的乘法可以简单地通过串联双极晶体管结的连接来提供，在该点处，所述电流被提供给相应的发射极。 在这种情况下，另外有利的是通过串联双极晶体管结的连接来产生参考信号，使得具有乘法器和发生器的类似行为。

公开(公告)号：EP0709956A1

公开(公告)日：1996-05-01

申请号：EP94830502.4

申请日：1994-10-27

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Galli, Giovanni ,  Scilla, Giuseppe

IPC: H03F1/52

CPC classification number: H03F1/52

Abstract: This invention is directed to provide a method, and associated circuit, which can prevent the latch-down phenomenon in transistors protected from going out of their SOAs.
By supplementing the first protection circuit (against moving out of the SOA) with a second protection circuit which can drive the control terminal of the transistor such that when, upon the voltage across the main conduction path of the transistor being increased, the value of the current flowing through said path would tend, due to the first protection, to drop below a predetermined lower limit, that value can be kept approximately constant and unaffected by the load as seen from the output terminal of the transistor; the transistor will at all events supply the load with some current up to the acceptable limit VMAX by the transistor.

Abstract translation: 本发明涉及提供一种方法和相关联的电路，它可以防止在晶体管闩锁向下现象外出他们的SOA的保护。 通过补充所述第一保护电路（针对移出SOA的）与第二保护电路，该电路可以驱动晶体管搜索那样的控制端子时，在跨越所述晶体管的主传导路径上的电压的增大，的值 电流流过所述路径将趋向，由于第一保护，下降到低于规定的下限值，没有值可以保持通过从晶体管的输出端看到的负载大致恒定和未受影响; 晶体管将在所有的事件与由所述晶体管一些电流至可接受的限度VMAX为负载供电。

公开(公告)号：EP0675431A1

公开(公告)日：1995-10-04

申请号：EP94830158.5

申请日：1994-03-31

Applicant: CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Abruzzese, Massimo ,  Giacalone, Biagio

IPC: G06F7/60

CPC classification number: G06N7/04 ,  Y10S706/90

Abstract: Memorization method in an electronic controller operating with fuzzy logic procedures for membership functions (FA) of logical variables (M) defined in a so-called discourse universe (U) discretized at a finite number of points (m) which provide memorization of triangular or trapezoid membership functions (FA) by means of memory words comprising a first portion in which is contained a codification of the vertex of the membership function (FA) and a second portion containing a codification corresponding to the slope of at least one side of the membership function (FA) as well as a third portion containing a codification corresponding to the slope of at least one other side of the function.

Abstract translation: 在以有限数量的点（m）分离的所谓的话语宇宙（U）中定义的逻辑变量（M）的隶属函数（FA）的模糊逻辑程序的记忆方法，其提供三角形或 借助于包含第一部分的存储单词的梯形隶属函数（FA），其中包含隶属函数（FA）的顶点的编码，以及包含对应于成员资格的至少一侧的斜率的编码的第二部分 功能（FA）以及包含对应于功能的至少另一侧的斜率的编码的第三部分。