公开(公告)号：US20030225962A1

公开(公告)日：2003-12-04

申请号：US10435594

申请日：2003-05-12

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Seisuke Hirosawa

IPC: G06F012/00

CPC classification number: G06F21/79 ,  G06F2221/2143

Abstract: The present invention provides a memory card realizing a simplified erasing process and shortened process time as a whole and capable of preventing an illegal access to the memory card discarded, and a system using the memory card. A system includes a flash memory card and a host device which is electrically connected to the flash memory card and controls the operation of the flash memory card. The system includes an erase command for executing an operation of erasing information in a data area in a flash memory and, in addition, a purge command for executing an operation of erasing all of information in the data area and a management information area in the flash memory. The purge command is issued by the host device to the flash memory card, thereby enabling the whole areas in the flash memory to be erased by the single issue of the purge command without issuing the erase command a plurality of times.

Abstract translation: 本发明提供了一种实现简化的擦除处理并缩短处理时间并且能够防止非法访问被丢弃的存储卡的存储卡，以及使用该存储卡的系统。 系统包括闪存卡和电连接到闪存卡并控制闪存卡的操作的主机设备。 该系统包括擦除命令，用于执行擦除闪速存储器中的数据区域中的信息的操作，此外，还包括用于执行擦除数据区域中的所有信息的操作和闪存中的管理信息区域的清除命令 记忆。 清除命令由主机发送到闪存卡，从而使闪存中的整个区域能够通过单次发出清除命令而被擦除，而不会多次发出擦除命令。

公开(公告)号：US20030206451A1

公开(公告)日：2003-11-06

申请号：US10419228

申请日：2003-04-21

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Toshihiro Tanaka ,  Yutaka Shinagawa ,  Kazufumi Suzukawa ,  Masamichi Fujito ,  Takashi Yamaki ,  Kiichi Makuta ,  Masashi Wada ,  Yoshiki Kawajiri

IPC: G11C029/00

CPC classification number: G11C16/3459 ,  G11C16/12 ,  G11C2216/14

Abstract: Disclosed is a nonvolatile memory with a shortened total write time, capable of stably writing data by making a write current constant while reducing fluctuations in a voltage generated by a booster circuit. In a nonvolatile memory such as a flash memory, data is determined at the time of writing operation. While skipping a bit corresponding to write data having the logic null1null (or logic null0null), writing operation to bits corresponding to write data having the logic null1null (or logic null1) is successively performed.

Abstract translation: 公开了一种具有缩短的总写入时间的非易失性存储器，能够通过使写入电流恒定而稳定地写入数据，同时减少由升压电路产生的电压的波动。 在诸如闪速存储器的非易失性存储器中，在写入操作时确定数据。 当对应于具有逻辑“1”（或逻辑“0”）的写入数据的位跳过时，对与具有逻辑“1”（或逻辑“1”的写入数据相对应的位进行写操作）。

公开(公告)号：US20030202381A1

公开(公告)日：2003-10-30

申请号：US10424855

申请日：2003-04-29

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Yuki Matsuda ,  Kenya Otani ,  Minoru Kato ,  Takeo Kon

IPC: G11C016/10

CPC classification number: G11C16/32 ,  G11C16/30

Abstract: The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic. The controller enables an information storage operation to the nonvolatile memory cells, by means of erase and write processing through boosting of the voltage applied to the nonvolatile memory cells and clamping of the boosted voltage, and performs a selection control that selects the application interval of the boosted voltage applied during the information storage operation and so forth. This selection control enables utilizing the nonvolatile memory cells as temporary rewrite areas, and facilitates to meet both of the mode of use that finds precedence in data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention characteristic.

Abstract translation: 本发明有助于满足在频繁重写期间优先使用的非易失性存储器的使用模式和在断开电源期间的数据保持，以及在数据保持特性中优先使用的使用模式。 控制器通过增加施加到非易失性存储单元的电压和钳位升压电压的擦除和写入处理，使得能够对非易失性存储单元进行信息存储操作，并执行选择控制，该选择控制选择 在信息存储操作期间施加的升压电压等等。 该选择控制使得能够将非易失性存储单元用作临时重写区域，并且有助于满足在断开电源期间在数据保持中优先使用的使用模式以及在数据保留中优先使用的使用模式 特性。

公开(公告)号：US20030141905A1

公开(公告)日：2003-07-31

申请号：US10345242

申请日：2003-01-16

Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co.,Ltd.

Inventor： Yoshikazu Saitou ,  Kenichi Osada

IPC: H03K019/094

CPC classification number: H03K19/0016

Abstract: The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.

Abstract translation: 本发明旨在简化用于在抑制亚阈值电流的同时固定逻辑门的输出逻辑的电路。 逻辑电路具有能够根据输入控制信号中断对逻辑门的电源的n沟道型第一晶体管，以及能够将逻辑门的输出节点固定为高电平的p沟道型第二晶体管 与第一晶体管的电源中断操作互锁，并且将第一晶体管的阈值设置为高于作为逻辑门的组件的晶体管的阈值。 用于中断对逻辑门的电源的装置由第一晶体管实现，并且通过第二晶体管实现将逻辑门的输出节点固定为高电平的装置，从而简化用于固定逻辑门的输出逻辑的电路 同时抑制亚阈值电流。

公开(公告)号：US20020024062A1

公开(公告)日：2002-02-28

申请号：US09886026

申请日：2001-06-22

Applicant: Hitachi, Ltd. Hitachi ULSI Systems Co., Ltd.

Inventor： Shigeru Nakahara ,  Hideki Hayashi ,  Takeshi Suzuki ,  Keiichi Higeta

IPC: H01L031/0328

CPC classification number: G11C29/848 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50012 ,  G11C29/787 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the setting information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide with each other.

Abstract translation: 一种其中具有多个存储器的半导体集成电路，通过有效地修复存储器中的有缺陷的位来实现提高的产量。 该半导体集成电路具有：多个电路块（RAM宏单元），每个电路块具有识别码重合检测电路，用于确定输入的识别码是否与自身识别码一致;以及接收数据锁存器，并执行根据 锁定数据; 设置电路，其能够设置与识别码相对应的识别码和信息，并且串行地输出设定信息; 以及控制电路，其能够从设置电路顺序读取设置信息，将设置信息转换为并行数据，并将并行数据传送到多个电路块。 当识别码重合检测电路确定输入的识别码和自识别码彼此一致时，多个电路块中的每一个捕获并保持传送的设置信息。

公开(公告)号：US20020014686A1

公开(公告)日：2002-02-07

申请号：US09915375

申请日：2001-07-27

Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.

Inventor： Kouichi Kanemoto ,  Masachika Masuda ,  Tamaki Wada ,  Michiaki Sugiyama ,  Mikako Kimura

IPC: H01L023/02

CPC classification number: H01L21/6836 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68327 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01028 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A first semiconductor chip (2) is bonded and secured to a second semiconductor chip (3) with a back surface of the first semiconductor chip (2) and a circuit forming surface (3X) of the second semiconductor chip (3) facing each other, and an inner portion of a support lead (6) is bonded and secured to the circuit forming surface (3X) of the second semiconductor chip (3). Such a configuration makes it possible to provide a semiconductor with a reduced thickness.

公开(公告)号：US20140225189A1

公开(公告)日：2014-08-14

申请号：US14259702

申请日：2014-04-23

Applicant: RENESAS ELECTRONICS CORPORATION ,  HITACHI ULSI SYSTEMS CO., LTD.

Inventor： Sumito NUMAZAWA ,  Yoshito NAKAZAWA ,  Masayoshi KOBAYASHI ,  Satoshi KUDO ,  Yasuo IMAI ,  Sakae KUBO ,  Takashi SHIGEMATSU ,  Akihiro OHNISHI ,  Kozo UESAWA ,  Kentaro OISHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/28114 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/0696 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Abstract translation: 在制造具有沟槽栅极结构的MISFET的半导体器件的方法中，从半导体层的方向的深度方向上的第一导电类型的半导体层的主表面形成沟槽， 在沟槽的内表面上形成包括热氧化膜和沉积膜的栅极绝缘膜，并且在沟槽中形成栅电极之后，将杂质引入到第一导电类型的半导体衬底中以形成 用作沟道形成区域的第二导电类型的半导体区域，并且将杂质引入到第二导电类型的半导体区域中，以形成用作源极区域的第一导电类型的半导体区域。

公开(公告)号：US08698224B2

公开(公告)日：2014-04-15

申请号：US13867055

申请日：2013-04-20

Applicant: Renesas Electronics Corporation ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Toshihiro Tanaka ,  Yukiko Umemoto ,  Mitsuru Hiraki ,  Yutaka Shinagawa ,  Masamichi Fujito ,  Kazufumi Suzukawa ,  Hiroyuki Tanikawa ,  Takashi Yamaki ,  Yoshiaki Kamigaki ,  Shinichi Minami ,  Kozo Katayama ,  Nozomu Matsuzaki

IPC: H01L29/788

CPC classification number: G11C16/26 ,  G11C5/025 ,  G11C8/08 ,  G11C16/04 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  H01L21/28 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/7885 ,  H01L29/792

Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc

Abstract translation: 半导体器件包括多个非易失性存储单元（1）。 每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。 第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。 第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。 第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。 假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

公开(公告)号：US20040205426A1

公开(公告)日：2004-10-14

申请号：US10808285

申请日：2004-03-25

Applicant: Hitachi, Ltd. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Masaya Muranaka ,  Hideaki Kato ,  Yutaka Ito

IPC: G06F011/00

CPC classification number: G06F11/1008 ,  G06F2201/88 ,  G06F2211/109 ,  G11C7/1006 ,  G11C29/42

Abstract: There is provided an error rate select circuit activated in an information sustaining mode, wherein a plurality of pieces of data is read out from a memory circuit comprising dynamic memory cells and inspection bits for detection and correction of an error existing in the pieces of data are generated. The inspection bits are stored in an additional memory circuit. An ECC circuit reads out the pieces of data from the memory circuit and the inspection bits associated with the pieces of data from the additional memory circuit to detect and correct an error existing in the pieces of data at fixed refresh intervals. If no error is detected, a first detection signal is accumulated in a first direction, that is, the first detection signal is added to a sum. If an error is detected, on the other hand, a second detection signal is accumulated in a second direction, that is, the second direction signal is multiplied by a weight to give a product before subtracting the product from the sum wherein the weight is large enough to result in a value of the product greater than the first detection signal. If the sum increases in the first direction, exceeding a predetermined value, the refresh period is lengthened by a predetermined incremental time. If the sum decreases in the second direction, becoming smaller than another predetermined value, on the other hand, the refresh period is shortened by a predetermined decremental time.

Abstract translation: 提供了在信息维持模式下激活的错误率选择电路，其中从包括动态存储单元的存储器电路读出多条数据，并且检测和校正存在于数据中的错误的检查位是 生成。 检查位存储在附加存储器电路中。 ECC电路从存储器电路读取数据以及与来自附加存储器电路的数据相关联的检查位，以固定的刷新间隔检测和校正存在于数据中的错误。 如果没有检测到错误，则在第一方向上累积第一检测信号，即，将第一检测信号加到和。 另一方面，如果检测到错误，则在第二方向上累积第二检测信号，即，将第二方向信号乘以权重，从而从重量大的和减去乘积之前给出乘积 足以导致产品的值大于第一检测信号。 如果总和在第一方向上增加超过预定值，则刷新周期被延长预定的增量时间。 如果总和在第二方向上减小，则变得小于另一个预定值，另一方面，刷新周期缩短预定的递减时间。

公开(公告)号：US20040196080A1

公开(公告)日：2004-10-07

申请号：US10823664

申请日：2004-04-14

Applicant: Renesas Technology Corp. ,  Hitachi ULSI Systems Co., Ltd.

Inventor： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

IPC: H03L007/06

CPC classification number: G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

Abstract: In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.