Abstract:
A method and system for providing and utilizing a magnetic memory are described. The magnetic memory includes a plurality of magnetic storage cells. Each magnetic storage cell includes magnetic element(s) programmable due to spin transfer when a write current is passed through the magnetic element(s) and selection device(s). The method and system include driving a first current in proximity to but not through the magnetic element(s) of a portion of the magnetic storage cells. The first current generates a magnetic field. The method and system also include driving a second current through the magnetic element(s) of the portion of the magnetic storage cells. The first and second currents are preferably both driven through bit line(s) coupled with the magnetic element(s). The first and second currents are turned on at a start time. The second current and the magnetic field are sufficient to program the magnetic element(s).
Abstract:
A method and system for providing and using a magnetic storage cell and magnetic memory is described. The method and system include providing a magnetic element and providing a selection device. The magnetic element is programmable to a first state by a first write current driven through the magnetic element in a first direction and to a second state by a second write current driven through the magnetic element in a second direction. The selection device is connected with the magnetic element. The selection device includes a gate having an aperture therein. The selection device is configured such that the first write current and second write current are provided to the magnetic element across the aperture.
Abstract:
Techniques and device designs associated with devices having magnetic or magnetoresistive tunnel junctions (MTJs) configured to operate based on spin torque transfer switching. On-plug MTJ designs and fabrication techniques are described.
Abstract:
A method and system for providing a magnetic memory is disclosed. The method and system include providing a plurality of magnetic storage cells in an array, a plurality of bit lines, and at least one bias structure. Each of the plurality of magnetic storage cells includes at least one magnetic element having an easy axis and being programmable by at least one write current driven through the magnetic element. The plurality of bit lines corresponds to the plurality of magnetic storage cells. The at least one bias structure is magnetically coupled with the at least one magnetic element in each of the plurality of magnetic storage cells. The at least one bias structure provides a bias field in a direction greater than zero degrees and less than one hundred eighty degrees from the easy axis.
Abstract:
A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above a threshold is passed through the first free layer. The free layer includes a low saturation magnetization material.
Abstract:
A CODEC 5 compresses and encodes a motion picture captured at a high speed of 240 Q)S frame rate in MPEG format. The CODEC 5 divides pictures in each frame into I pictures and the main frame P pictures (P4, P8, P 12) and the other sub frame P pictures (pi, p2, p3, ...). In encoding P pictures of the main frame, the CODEC 5 uses I pictures that are adjacent on the time axis or P pictures of other main frames as a reference picture. With a playback device, etc., of its motion picture playback performance of 60 fps, to perform an actual speed playback with the playback time being equal to the picture-capturing time, only the main frame alone is to be subjected to playback, in that case the decoding process of P pictures of the sub frames is not required.
Abstract:
A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programmed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.
Abstract:
A method of producing ultra shallow junctions (104) for PMOS transistors, which eliminates the need for pre-amorphization implants, is disclosed. The method utilizes octadecaborane, B 18 H 22 . In accordance with the present invention, the pre-amorphizing step may be eliminated, greatly reducing cost per processed wafer. An appropriate process sequence has been suggested to take advantage of cluster ion implantation for PMOS manufacturing. In addition, the novel use of tilted implants for the source/drain extension and for pocket implants has been described.
Abstract:
A method and system for providing a magnetic memory including a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Magnetic element(s) are programmable using write current(s) driven through the magnetic element. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. A first stage converts at least current signal to at least one differential voltage signal. A second stage amplifies the at least one differential voltage signal. The logic selectively disables at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.
Abstract:
A squib driver module comprises a squib circuit for deploying a squib, e.g., in an airbag assembly, the squib circuit including a high side driver and a low side driver in combination for driving a firing signal to the squib: a circuit for activating the firing signal in response to a firing condition; squib diagnostic circuits for conducting diagnostic tests without activating the firing signal and without delivering a diagnostic signal equivalent of the firing signal to the squib, and for generating digital fault information based on the tests; registers for storing the fault information; logic for recognizing a fault condition based on the fault information; and a communication module for communicating the fault condition to a microprocessor unit. The squib diagnostic circuit may include node voltage diagnostic circuits, USD and/or LSD open/short circuits, USD and/or LSD driver fault diagnostic circuits, squib-squib short diagnostic circuits, and/or squib resistance diagnostic circuits.