公开(公告)号：WO2012115744A1

公开(公告)日：2012-08-30

申请号：PCT/US2012/022823

申请日：2012-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORP. ,  BIVENS, John A. ,  FRANCESCHINI, Michele M. ,  LASTRAS-MONTANO, Luis A.

Inventor： BIVENS, John A. ,  FRANCESCHINI, Michele M. ,  LASTRAS-MONTANO, Luis A.

IPC: G06F13/00

CPC classification number: G11C7/1012 ,  G06F2213/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/008

Abstract: A memory system that includes a plurality of memory arrays having memory cells characterized by a variable write time. The memory system also includes a memory bus configured to receive write commands, and a plurality of data buffers configured to communicate with the memory arrays. The memory system further includes an address buffer configured to communicate with the memory arrays to store the write addresses. A mechanism configured to receive a write command and to split a data line received with the write command into a number of parts is also included in the memory system. The parts of the data line are stored in different data buffers and the writing of the parts of the data line to memory arrays at the write address is initiated. The write command is completed when write completion signals specifying the write address have been received from all of the memory arrays.

Abstract translation: 一种存储器系统，其包括具有由可变写入时间表征的存储器单元的多个存储器阵列。 存储器系统还包括被配置为接收写入命令的存储器总线以及被配置为与存储器阵列进行通信的多个数据缓冲器。 存储器系统还包括配置为与存储器阵列通信以存储写入地址的地址缓冲器。 被配置为接收写入命令并将用写入命令接收的数据线分割成多个部件的机构也包括在存储器系统中。 数据线的部分存储在不同的数据缓冲器中，并且开始将写入地址的数据线的部分写入存储器阵列。 当从所有存储器阵列接收到指定写入地址的写入完成信号时，写入命令完成。

公开(公告)号：WO2012089507A3

公开(公告)日：2012-07-05

申请号：PCT/EP2011/072734

申请日：2011-12-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  MEANEY, Patrick, James ,  JOHNSON, Judy ,  STEPHENS, Eldee ,  LASTRAS-MONTANO, Luis

Inventor： MEANEY, Patrick, James ,  JOHNSON, Judy ,  STEPHENS, Eldee ,  LASTRAS-MONTANO, Luis

IPC: G06F11/10

Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

公开(公告)号：WO2011160923A1

公开(公告)日：2011-12-29

申请号：PCT/EP2011/058924

申请日：2011-05-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  MEANEY, Patrick, James ,  LASTRAS-MONTANO, Luis ,  STEPHENS, Eldee ,  PAPAZOVA, Vesselina ,  GOWER, Kevin

Inventor： MEANEY, Patrick, James ,  LASTRAS-MONTANO, Luis ,  STEPHENS, Eldee ,  PAPAZOVA, Vesselina ,  GOWER, Kevin

IPC: G06F11/20 ,  G06F11/14

CPC classification number: G06F11/1666 ,  G06F11/1044 ,  G06F11/108 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/20 ,  G06F11/2007 ,  G06F2211/1088

Abstract: Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.

Abstract translation: 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作，并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。

公开(公告)号：WO2010097302A1

公开(公告)日：2010-09-02

申请号：PCT/EP2010/051786

申请日：2010-02-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FRANCESCHINI, Michele, Martino ,  LASTRAS-MONTANO, Luis ,  KARIDIS, John, Peter

Inventor： FRANCESCHINI, Michele, Martino ,  LASTRAS-MONTANO, Luis ,  KARIDIS, John, Peter

IPC: G11C11/56 ,  G11C16/02

CPC classification number: G11C13/004 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C2013/0052

Abstract: Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In a preferred embodiment of the present invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.

Abstract translation: 读取相变存储器的技术，减轻电阻漂移。 一种预期的方法包括将多个电输入信号应用于存储器单元。 该方法包括从多个电输入信号测量来自存储器单元的多个电输出信号。 该方法包括根据存储单元中非晶材料的配置来计算多个电输出信号的不变分量。 该方法还包括基于不变分量来确定存储器单元的存储器状态。 在本发明的优选实施例中，该方法还包括将多个电输出信号映射到多个测量区域的测量区域。 测量区域对应于存储器单元的存储器状态。

公开(公告)号：WO2010097257A1

公开(公告)日：2010-09-02

申请号：PCT/EP2010/050797

申请日：2010-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LASTRAS-MONTANO, Luis ,  FRANCESCHINI, Michele ,  LAM, Chung, Hon ,  RAJENDRAN, Bipin

Inventor： LASTRAS-MONTANO, Luis ,  FRANCESCHINI, Michele ,  LAM, Chung, Hon ,  RAJENDRAN, Bipin

IPC: G11C15/00 ,  G11C15/02 ,  G11C15/04

CPC classification number: G11C15/00 ,  G11C7/1006 ,  G11C13/0004 ,  G11C15/02 ,  G11C15/046

Abstract: A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.

Abstract translation: 使用编码数据字和搜索词的内容可寻址存储器，以及用于操作这样的设备的技术。 在一个实施例中，当数据字与搜索词不匹配时，数据字被转换成保证在存储器搜索操作期间不同二进制值的至少两个码字位的失配的码字。 在另一个实施例中，搜索词被变换成搜索码，使得当数据字和搜索词之间存在至少一个比特的不匹配时，码字和搜索码之间的汉明距离大于给定阈值 。

公开(公告)号：WO2009000639A3

公开(公告)日：2009-05-28

申请号：PCT/EP2008057199

申请日：2008-06-10

Applicant: IBM ,  IBM UK ,  ALVES LUIZ ,  CLARKE WILLIAM ,  DELL TIMOTHY ,  DEWKETT THOMAS ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS ,  O CONNOR JAMES

Inventor： ALVES LUIZ ,  CLARKE WILLIAM ,  DELL TIMOTHY ,  DEWKETT THOMAS ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS ,  O CONNOR JAMES

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F2211/1045 ,  G06F2211/1057 ,  G06F2211/1064

Abstract: A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.

Abstract translation: 一种用于存储系统中的纠错和检测的系统和方法。 该系统包括存储器控制器，多个存储器模块和机构。 存储器模块与存储器控制器和多个存储器件通信。 该机制检测到其中一个内存模块出现故障，可能与其他内存模块上的内存设备故障一致。 该机制允许内存系统在内存模块故障和内存设备故障的情况下继续运行不受损坏。