中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.023 seconds)

    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM
    3.
    发明申请
    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM 审中-公开
    用于在压缩存储器系统中显示存储器重组工作的延迟的系统和方法

    公开(公告)号：WO2008030672A2

    公开(公告)日：2008-03-13

    申请号：PCT/US2007/074721

    申请日：2007-07-30

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DALY, David, Michael ,  FRANASZEK, Peter, Anthony ,  IGNATOWSKI, Michael ,  LASTRAS-MONTANO, Luis, Alfonso ,  TROMBLEY, Michael, Raymond

    Inventor： DALY, David, Michael ,  FRANASZEK, Peter, Anthony ,  IGNATOWSKI, Michael ,  LASTRAS-MONTANO, Luis, Alfonso ,  TROMBLEY, Michael, Raymond

    CPC classification number: G06F12/08 ,  G06F12/0804 ,  G06F12/1408 ,  G06F2212/401

    Abstract: Computer memory management systems and methods are provided hi which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory, to particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory.reorganization work to allow resources to be used for serving new memory access requests and other high priority commands. In one aspect, a computer system ( 10) includes a main memory ( 160) comprising first (161) and second (162) memory' regions having different access characteristics, a memory controller (130) to manage the main memory (160) and to allow access to stored data items in the main memory (160), wherein the memory controller ( 130) implements a memory reorganization process comprising an execution flow of process steps for accessing a data hem that is stored in one of the first (161) or second memory region (162), and storing the accessed data item in the other one of the first (161) or second (162) memory region, and a local buffer memory (150) operated under control of the memory controller (130) to temporarily buffer data items to be written to the main memory (160) and data items read from the main memory (160) during the memory reorganization process, wherein the memory controller (130) temporarily suspends the execution flow of the memory reorganization process between process steps, if necessary, according to a priority schedule, and utilizes the local buffer memory (150) to temporarily store data that is to be processed when the memory reorganization process is resumed

    Abstract translation: 提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的延迟，特别是数据块缓冲器和优先级调度协议 实现延迟和优先级的内存。组织工作，以允许资源用于提供新的内存访问请求和其他高优先级命令。 一方面，一种计算机系统（10）包括主存储器（160），该主存储器包括具有不同访问特性的第一（161）和第二（162）存储器区域，存储器控制器（130），用于管理主存储器（160）和 以允许访问主存储器（160）中的存储的数据项，其中存储器控制器（130）实现存储器重组过程，其包括用于访问存储在第一（161）中的一个中的一个中的数据帧的处理步骤的执行流程， 或第二存储器区域（162），并且将访问的数据项存储在第一（161）或第二（162）存储区域中的另一个存储器区域中，以及在存储器控制器（130）的控制下操作的本地缓冲存储器（150） 在存储器重组处理期间临时缓冲要写入主存储器（160）的数据项和从主存储器（160）读取的数据项，其中存储器控制器（130）暂时中止存储器重组过程的执行流程 流程步骤，我 f根据优先级调度，并且利用本地缓冲存储器（150）临时存储当重新开始存储器重组处理时要被处理的数据

    FAILING BUS LANE DETECTION USING SYNDROME ANALYSIS
    5.
    发明申请
    FAILING BUS LANE DETECTION USING SYNDROME ANALYSIS 审中-公开
    使用综合分析故障总线检测

    公开(公告)号：WO2011160956A1

    公开(公告)日：2011-12-29

    申请号：PCT/EP2011/059533

    申请日：2011-06-08

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  LASTRAS-MONTANO, Luis ,  MEANEY, Patrick, James ,  GOWER, Lisa

    Inventor： LASTRAS-MONTANO, Luis ,  MEANEY, Patrick, James

    IPC: G06F11/10 ,  H03M13/09 ,  H04L1/00

    CPC classification number: G06F11/10 ,  H03M13/09 ,  H04L1/0061 ,  H04L1/24 ,  H04L2001/0094

    Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

    Abstract translation: 包括用于接收错误检测码的多个综合征的方法，所述错误检测码与已经在包括多个车道的总线上发送并被由多个车道保护的多个帧相关联的错误检测码 错误检测码。 该方法包括对每个综合征中的每个通道执行：在所述通道是故障通道的假设下解码所述综合征，所述解码输出解码结果; 确定解码结果是否是有效的解码; 并且响应于确定解码结果是有效解码而对该通道进行投票。 然后，响应于投票，确定失败的车道，失败的车道的特征在于比公车上的至少另一个车道具有更多的票数。

    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK
    6.
    发明申请
    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK 审中-公开
    循环冗余码用于高速串行链路

    公开(公告)号：WO2010000623A3

    公开(公告)日：2010-02-25

    申请号：PCT/EP2009057580

    申请日：2009-06-18

    Applicant: IBM ,  IBM UK ,  DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

    Inventor： DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

    IPC: G06F11/00

    CPC classification number: H04L1/0056 ,  G06F11/10

    Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

    Abstract translation: 一种用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。 该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。 下游链路与存储器控制器和存储器集线器设备通信，并且包括用于将多个传输下行帧从存储器控制器发送到存储器集线器设备的至少十三个信号通道。 下游帧的一部分包括用于检测下游帧中的错误的下行CRC位。 下行CRC比特能够检测到车道故障，转移故障和高达五位随机错误中的任何一个。

    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM
    7.
    发明申请
    SYSTEMS AND METHODS FOR MASKING LATENCY OF MEMORY REORGANIZATION WORK IN A COMPRESSED MEMORY SYSTEM 审中-公开
    用于掩蔽压缩存储器系统中存储器重组延迟的系统和方法

    公开(公告)号：WO2008030672A3

    公开(公告)日：2008-05-08

    申请号：PCT/US2007074721

    申请日：2007-07-30

    Applicant: IBM ,  DALY DAVID MICHAEL ,  FRANASZEK PETER ANTHONY ,  IGNATOWSKI MICHAEL ,  LASTRAS-MONTANO LUIS ALFONSO ,  TROMBLEY MICHAEL RAYMOND

    Inventor： DALY DAVID MICHAEL ,  FRANASZEK PETER ANTHONY ,  IGNATOWSKI MICHAEL ,  LASTRAS-MONTANO LUIS ALFONSO ,  TROMBLEY MICHAEL RAYMOND

    IPC: G06F12/08

    CPC classification number: G06F12/08 ,  G06F12/0804 ,  G06F12/1408 ,  G06F2212/401

    Abstract: Computer memory management systems and methods are provided hi which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory, to particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory.reorganization work to allow resources to be used for serving new memory access requests and other high priority commands. In one aspect, a computer system ( 10) includes a main memory ( 160) comprising first (161) and second (162) memory' regions having different access characteristics, a memory controller (130) to manage the main memory (160) and to allow access to stored data items in the main memory (160), wherein the memory controller ( 130) implements a memory reorganization process comprising an execution flow of process steps for accessing a data hem that is stored in one of the first (161) or second memory region (162), and storing the accessed data item in the other one of the first (161) or second (162) memory region, and a local buffer memory (150) operated under control of the memory controller (130) to temporarily buffer data items to be written to the main memory (160) and data items read from the main memory (160) during the memory reorganization process, wherein the memory controller (130) temporarily suspends the execution flow of the memory reorganization process between process steps, if necessary, according to a priority schedule, and utilizes the local buffer memory (150) to temporarily store data that is to be processed when the memory reorganization process is resumed

    Abstract translation: 提供计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩蔽与访问压缩主存储器之后的存储器重组工作相关的等待时间，特别是数据块缓冲器和优先级调度协议 实现延迟和优先化memory.reorganization工作，以允许资源用于服务新的内存访问请求和其他高优先级命令。 在一个方面中，一种计算机系统（10）包括：主存储器（160），其包括具有不同访问特性的第一存储区（161）和第二存储区（162）;管理主存储器（160）的存储器控​​制器（130）;以及 以允许访问主存储器（160）中存储的数据项，其中存储器控制器（130）实现存储器重组过程，该存储器重组过程包括用于访问存储在第一（161）中的一个中的数据卷边的处理步骤的执行流程， 或第二存储器区域（162）中，并且将访问的数据项存储在第一（161）或第二（162）存储器区域中的另一个中，以及在存储器控制器（130）的控制下操作的本地缓冲存储器（150） 在存储器重新组织过程期间临时缓存要写入主存储器（160）的数据项和从主存储器（160）读取的数据项，其中存储器控制器（130）暂时中止存储器重组过程的执行流程 过程步骤，i f根据优先级调度表，并且利用本地缓冲存储器（150）临时存储当恢复存储器重组过程时要处理的数据

    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK
    9.
    发明申请
    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK 审中-公开
    用于高速串行链路的循环冗余码

    公开(公告)号：WO2010000623A4

    公开(公告)日：2010-04-22

    申请号：PCT/EP2009057580

    申请日：2009-06-18

    Applicant: IBM ,  IBM UK ,  DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

    Inventor： DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

    IPC: G06F11/00

    CPC classification number: H04L1/0056 ,  G06F11/10

    Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

    Abstract translation: 一种用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。 该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。 下游链路与存储器控制器和存储器集线器设备通信并且包括至少十三条信道，用于从存储器控制器向存储器集线器设备传输多传送下游帧。 下游帧的一部分包括下游CRC比特以检测下游帧中的错误。 下行CRC位能够检测到通道故障，传输故障和高达5位随机错误中的任何一个。

    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK
    10.
    发明申请
    CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK 审中-公开
    用于高速串行链路的循环冗余码

    公开(公告)号：WO2010000623A2

    公开(公告)日：2010-01-07

    申请号：PCT/EP2009/057580

    申请日：2009-06-18

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  DELL, Timothy ,  GOWER, Kevin ,  LASTRAS-MONTANO, Luis

    Inventor： DELL, Timothy ,  GOWER, Kevin ,  LASTRAS-MONTANO, Luis

    IPC: G06F11/00

    CPC classification number: H04L1/0056 ,  G06F11/10

    Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

    Abstract translation: 用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。 该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。 下游链路与存储器控制器和存储器集线器设备通信并且包括至少十三条信道，用于从存储器控制器向存储器集线器设备传输多传送下游帧。 下游帧的一部分包括下游CRC比特以检测下游帧中的错误。 下游CRC位能够检测到任何一个通道故障，传输故障和高达5位的随机错误。

Patent Agency Ranking