公开(公告)号：WO1997039471A1

公开(公告)日：1997-10-23

申请号：PCT/JP1997001342

申请日：1997-04-17

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  OMAE, Hideharu ,  KONDA, Masahiko ,  HIRABAYASHI, Kazuaki ,  OTANI, Mitsuhiro ,  NAKATERA, Shigeo

Inventor： MATSUSHITA ELECTRONICS CORPORATION ,  MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

IPC: H01J29/58

CPC classification number: H01J29/485 ,  H01J9/14

Abstract: A cathode-ray tube having an electron gun including a main focusing lens made of a helical high-resistance material, and a process for producing the same. The method of forming a helical high-resistance body on the inner surface of a glass tube comprises the steps of making (31) a hole in the central portion of the glass tube and attaching a sealing ring by fritting to carry out electrical connection to both ends of the glass tube, coating (35) the glass tube with a paste of a high-resistance material obtained by compounding glass powder having a softening point lower than an annealing temperature of the glass tube with ruthenium oxide, forming (37) a helical structure on a film of the high-resistance material after it has been dried, and baking (38) the resultant product at a temperature of 420 DEG C - 550 DEG C, whereby a helical high-resistance body having a resistance value of 0.8 G OMEGA - 100 G OMEGA is formed.

Abstract translation: 一种具有电子枪的阴极射线管及其制造方法，该电子枪包括由螺旋状高电阻材料制成的主聚焦透镜。 在玻璃管的内表面上形成螺旋状高阻体的方法包括以下步骤：在玻璃管的中心部分形成（31）孔，并通过烧结连接密封环，以实现与两者的电连接 玻璃管的端部，通过将软化点低于玻璃管的退火温度的玻璃粉末与氧化钌混合而获得的高电阻材料的糊料涂覆（35）玻璃管，形成（37）螺旋 在高电阻材料的膜被干燥之后的结构，并在420℃-550℃的温度下烘烤（38）所得产物，由此得到具有电阻值为0.8G的螺旋状高电阻体 OMEGA - 100 G OMEGA形成。

公开(公告)号：WO1997034320A1

公开(公告)日：1997-09-18

申请号：PCT/US1997004185

申请日：1997-03-14

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  MCMILLAN, Larry, D. ,  SCOTT, Michael, C. ,  PAZ DE ARAUJO, Carlos, A. ,  OTSUKI, Tatsuo ,  HAYASHI, Shinichiro

IPC: H01L21/316

CPC classification number: H01L21/316 ,  B05D1/00 ,  B05D1/60 ,  B05D3/0493 ,  C23C16/4412 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/1212 ,  C23C18/1287 ,  C23C18/14 ,  C23C26/02 ,  C30B7/00 ,  C30B29/68 ,  H01L21/314 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L41/316 ,  H05K3/105

Abstract: A precursor liquid (64) comprising silicon in a xylene solvent is prepared, a substrate (5, 71) is placed within a vacuum deposition chamber (2), the precursor liquid is misted, and the mist (66) is flowed into the deposition chamber while maintaining the chamber at ambient temperature to deposit a layer of the precursor liquid on the substrate. The liquid is dried, baked, and annealed to form a thin film (1224, 77) of silicon dioxide or silicon glass on the substrate. Then an integrated circuit (100) is completed to include at least a portion of the silicon dioxide or silicon glass layer as an insulator (77) for an electronic device (76) in the integrated circuit.

Abstract translation: 制备在二甲苯溶剂中含硅的前体液体（64），将基材（5,71）放置在真空沉积室（2）内，使前体液体雾化，并将雾（66）流入沉积物 同时将室保持在环境温度下，以将一层前体液体沉积在基底上。 将液体干燥，烘烤和退火，以在基底上形成二氧化硅或硅玻璃的薄膜（1224,77）。 然后，完成集成电路（100）以将至少一部分二氧化硅或硅玻璃层作为用于集成电路中的电子器件（76）的绝缘体（77）。

公开(公告)号：WO1997033013A1

公开(公告)日：1997-09-12

申请号：PCT/US1997003393

申请日：1997-03-04

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  HAYASHI, Shinichiro ,  MCMILLAN, Larry, D. ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A.

IPC: C23C26/02

CPC classification number: H01L21/02197 ,  B05D1/00 ,  B05D1/60 ,  B05D3/0493 ,  B05D3/062 ,  B05D3/065 ,  C23C8/10 ,  C23C16/4412 ,  C23C16/4486 ,  C23C16/45561 ,  C23C16/4558 ,  C23C16/46 ,  C23C16/482 ,  C23C16/52 ,  C23C18/12 ,  C23C18/1216 ,  C23C18/1287 ,  C23C18/14 ,  C23C26/02 ,  C30B7/00 ,  C30B7/005 ,  C30B29/68 ,  H01L21/02282 ,  H01L21/31691 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L41/1871 ,  H01L41/314 ,  H05K3/105

Abstract: A substrate (5) is located within a deposition chamber (2), the substrate defining a substrate plane. A barrier plate (6) is disposed in spaced relation above the substrate and substantially parallel thereto, the area of said barrier plate in a plane parallel to said substrate being substantially equal to said area of said substrate in said substrate plane, i.e. within 10 % of said substrate area. The barrier plate has a smoothness tolerance of 5 % of the average distance between said barrier plate and said substrate. A mist (66) is generated, allowed to settle in a buffer chamber (42), filtered through a 1 micron filter (33), and flowed into the deposition chamber between the substrate and barrier plate to deposit a liquid layer on the substrate. The liquid is dried to form a thin film (1130) of solid material on the substrate, which is then incorporated into an electrical component (1112) of an integrated circuit (1110).

Abstract translation: 衬底（5）位于沉积室（2）内，衬底限定衬底平面。 阻挡板（6）以基板间隔开的关系设置并且基本上平行于其上，所述阻挡板在与所述基板平行的平面中的面积基本上等于所述基板平面中的所述基板的面积，即在10％ 的所述衬底区域。 阻挡板具有所述阻挡板和所述基板之间的平均距离的5％的平滑度公差。 产生雾（66），允许沉淀在缓冲室（42）中，通过1微米过滤器（33）过滤，并流入基板和阻挡板之间的沉积室，以在基板上沉积液体层。 将液体干燥以在基板上形成固体材料的薄膜（1130），然后将其并入集成电路（1110）的电气部件（1112）中。

公开(公告)号：WO1997027622A1

公开(公告)日：1997-07-31

申请号：PCT/JP1997000151

申请日：1997-01-23

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  IMAI, Shinichi ,  NIKOH, Hideo ,  JIWARI, Nobuhiro

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: H01L21/3065

CPC classification number: H01L21/67069 ,  H01L21/3065

Abstract: A semiconductor manufacturing apparatus comprising a silicon ring (12), as a halogen scavenger, having an average surface roughness of 1-1,000 mu m around a silicon substrate (6) on a lower electrode (3) in a reaction chamber (7); and an upper silicon element (5), as another halogen scavenger, having an average surface roughness of 1-1,000 mu m above the substrate (6), wherein C2F6 gas is used in the chamber (7). In this apparatus, fluorine is effectively removed in the initial phase of operation, and semiconductor devices can be aged in a relatively short time.

Abstract translation: 一种半导体制造装置，包括作为卤素清除剂的硅环（12），其在反应室（7）中的下电极（3）上的硅衬底（6）周围具有1-1000μm的平均表面粗糙度; 和作为另一种卤素清除剂的上部硅元素（5），其具有在基板（6）上方的平均表面粗糙度为1-1000μm，其中在室（7）中使用C2F6气体。 在这种装置中，在初始操作阶段有效去除氟，半导体器件可以在较短时间内老化。

公开(公告)号：WO1997017731A1

公开(公告)日：1997-05-15

申请号：PCT/JP1996003274

申请日：1996-11-07

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  TANABE, Mitsuru

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: H01L29/812

CPC classification number: H01L29/66462 ,  H01L21/28587 ,  H01L29/7783

Abstract: A field effect transistor (100) comprising an InP substrate (10) on which are deposited an InA1As buffer layer (11), an InGaAs channel layer (12), an InA1As spacer layer (13), an A1GaAs carrier supplying layer (14), an InA1As Schottky layer (15), and an InGaAs cap layer (16) in this order. In addition, a source electrode (17s), a drain electrode (17d), and a gate electrode (18) are formed at prescribed places on the top of this multilayer structure. The carrier supplying layer (14) is composed of a material in which the silicon as a dopant cannot be terminated by fluorine. Therefore, the field effect transistor (100) can have a high transconductance without causing a decrease in the drain current.

Abstract translation: 包括InP衬底（10）的场效应晶体管（100），其上沉积有InAlAs缓冲层（11），InGaAs沟道层（12），InAlAs间隔层（13），AlGaAs载体供应层（14） ，InAlAs肖特基层（15）和InGaAs覆盖层（16）。 此外，在该多层结构的顶部的规定位置处形成源电极（17s），漏电极（17d）和栅电极（18）。 载体供给层（14）由作为掺杂剂的硅不能被氟端接的材料构成。 因此，场效应晶体管（100）可以具有高的跨导而不引起漏极电流的降低。

公开(公告)号：WO1997005660A1

公开(公告)日：1997-02-13

申请号：PCT/JP1996002142

申请日：1996-07-30

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  SANO, Yoshikazu ,  TERAKAWA, Sumio ,  TSUJII, Eiichi ,  ASAUMI, Masaji ,  CHATANI, Yoshikazu

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: H01L27/148

CPC classification number: H01L31/02002 ,  H01L27/14618 ,  H01L27/148 ,  H01L31/0203 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1815 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a solid-state image pickup device for high-picture-quality video cameras, which makes it easy to enclose a CCD chip in a resin, ceramic, or glass package, while eliminating the difficulty of optically accurate placement of the chip in a ceramic package or on the internal bottom of the package, achieving high yield to reduce manufacturing costs, and reducing the device size. In order to accomplish the above-mentioned purpose, a CCD chip (27) is inserted into a hole (26) opened in a package (21) in which a lead frame (24) composed of inner leads (22) and outer leads (23) is sealed. The chip is then optically aligned and electrically connected by connecting electrode pads (28) to the inner leads (22) through bumps (29), and fixed with a bonding agent. Therefore, the position of the chip (27) can be adjusted with extremely high accuracy. The solid-state image pickup device can be mounted on a high-picture-quality video camera that can reproduce fine pictures of clear colors and it can be manufactured at a low cost.

Abstract translation: 一种制造用于高画质摄像机的固态摄像装置的方法，其使得能够容易地将CCD芯片封装在树脂，陶瓷或玻璃封装中，同时消除了芯片的光学精确放置的难度 在陶瓷封装中或封装的内部底部，实现高产率以降低制造成本，并减小器件尺寸。 为了实现上述目的，将CCD芯片（27）插入到由内引线（22）和外引线（22）构成的引线框架（24）的封装（21）中开口的孔（26） 23）密封。 然后通过将电极焊盘（28）通过凸块（29）连接到内部引线（22）而将芯片光学对准并电连接，并用粘合剂固定。 因此，可以极高的精度来调整芯片（27）的位置。 固态图像拾取装置可以安装在可以再现清晰颜色的精细图像的高画质摄像机上，并且可以以低成本制造。

公开(公告)号：WO1996041375A1

公开(公告)日：1996-12-19

申请号：PCT/US1996009100

申请日：1996-06-06

Applicant: SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION

Inventor： SYMETRIX CORPORATION ,  MATSUSHITA ELECTRONICS CORPORATION ,  AZUMA, Masamichi ,  PAZ DE ARAUJO, Carlos, A. ,  CUCHIARO, Joseph, D.

IPC: H01L23/532

CPC classification number: H01L27/11502 ,  H01L23/53242 ,  H01L23/53252 ,  H01L28/55 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A thin-film ferroelectric capacitor (20) includes a bottom electrode structure (26) having an adhesion metal layer (36) and a noble metal portion (38). The electrode (26) is deposited over a thin-film buffer layer (24), which contains a layered superlattice material. The buffer layer is interposed between a substrate (22) and the bottom electrode (26). A process of manufacture includes deposition of a liquid precursor on the substrate (22) prior to formation of the bottom electrode (26).

Abstract translation: 薄膜强电介质电容器（20）包括具有粘附金属层（36）和贵金属部分（38）的底部电极结构（26）。 电极（26）沉积在包含层状超晶格材料的薄膜缓冲层（24）上。 缓冲层介于衬底（22）和底电极（26）之间。 一种制造方法包括在形成底部电极（26）之前在基底（22）上沉积液体前体。

公开(公告)号：WO1990013145A1

公开(公告)日：1990-11-01

申请号：PCT/JP1990000523

申请日：1990-04-23

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  ARAI, Katsujiro

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: H01L29/788

CPC classification number: H01L27/11526 ,  H01L27/0928 ,  H01L27/105 ,  H01L27/11546

Abstract: On a semiconductor substrate (101) is formed an epitaxial layer (102) of the conductive type opposite to that of the substrate. In the epitaxial layer (102) is formed an impurity diffused layer (103) of the same conductive type as that of the substrate that is so deep as to reach the semiconductor substrate. CMOS elements and functional elements are formed on the deep impurity diffused layer and on epitaxial layers (110, 111) surrounded by the deep impurity diffused layer. Further, in other epitaxial layers that are electrically isolated are formed impurity diffused layers (106, 108) that do not reach the semiconductor substrate, and CMOS elements and functional elements are formed thereon. This makes it possible to prevent the development of defective writing of EPROM formed on the same semiconductor substrate and to prevent the characteristics from being deteriorated by the back bias of analog circuits.

公开(公告)号：WO1998034285A1

公开(公告)日：1998-08-06

申请号：PCT/JP1997004916

申请日：1997-12-26

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  INOUE, Tomio ,  SANADA, Kenichi ,  KOYA, Kenichi ,  FUKUDA, Yasuhiko

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: H01L33/00

CPC classification number: H01L33/40 ,  H01L25/167 ,  H01L33/32 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49107 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A GaN LED element (1) having a double hetero structure composed of a GaN layer, etc., formed on a sapphire substrate is mounted on an Si diode element (2) formed on a silicon substrate in a face down bonding state. P- and n-electrodes (5 and 6) of the LED element (1) are respectively connected to n- and p-electrodes (8 and 7) of the diode element (2) through Au micro-bumps (11 and 12), and the diode element (2) protects the LED element (1) from electrostatic breakdown. A rear-surface electrode (9) of the diode element (2) is connected to a lead frame (13a), and a bonding pad section (10) of the p-electrode (7) of the diode element (2) is connected to another lead frame (13b) through an Au wire (17).

Abstract translation: 形成在蓝宝石衬底上的由GaN层等构成的双异质结构的GaN LED元件（1）以面向下接合状态安装在形成于硅衬底上的Si二极管元件（2）上。 LED元件（1）的P电极和N电极（5和6）分别通过Au微型突起（11和12）连接到二极管元件（2）的n电极和p电极（8和7） ，并且二极管元件（2）保护LED元件（1）免受静电破坏。 二极管元件（2）的背面电极（9）连接到引线框架（13a），并且二极管元件（2）的p电极（7）的接合焊盘部分（10）被连接 通过Au线（17）到另一个引线框架（13b）。

公开(公告)号：WO1997035314A1

公开(公告)日：1997-09-25

申请号：PCT/JP1997000882

申请日：1997-03-18

Applicant: MATSUSHITA ELECTRONICS CORPORATION ,  HIRANO, Hiroshige ,  ASARI, Koji

Inventor： MATSUSHITA ELECTRONICS CORPORATION

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A ferroelectric memory reading method capable of carrying out a low-voltage operation more reliably than a conventional method of this kind, and a ferroelectric memory are provided. In order to achieve the above objects, an operation for turning the electric potentials of bit lines BLO, /BLO into logical voltages "H", "L" respectively is carried out by a sense amplifier after a pulsatile cell plate signal CP has been applied to a cell plate electrode as shown in, for example, the figure. Namely, an electric field is temporarily applied to a ferroelectric capacitor, and then the application of a signal to the cell plate electrode is controlled so as not to apply the electric field to the same capacitor, the electric potentials of the bit lines being thereafter amplified by a sense amplifier.

Abstract translation: 提供了一种能够比常规方法更可靠地执行低电压操作的铁电存储器读取方法和强电介质存储器。 为了实现上述目的，在施加脉冲单元板信号CP之后，由位线BLO，/ BLO的电位分别转换为逻辑电压“H”，“L”的操作由读出放大器执行 到例如图中所示的电池板电极。 即，将电场临时施加到铁电电容器，然后控制向单元板电极施加信号，以不对同一电容器施加电场，然后位线的电位被放大 由感测放大器。