公开(公告)号：EP1732124B1

公开(公告)日：2016-09-14

申请号：EP06010424.7

申请日：2006-05-19

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

公开(公告)号：EP1729338A3

公开(公告)日：2009-04-15

申请号：EP06010091.4

申请日：2006-05-16

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10891

Abstract: Method for forming a semiconductor memory device with a recessed gate. A substrate (208), having a plurality of deep trench capacitors (206) therein, is provided wherein upper portions of the deep trench capacitor devices are revealed. Spacers (226) on sidewalls of the upper portions of the deep trench capacitors are formed to form a predetermined region surrounded by the deep trench capacitor devices. The predetermined region of the substrate is etched using the spacers and the upper portions of the deep trench capacitors serve as a mask to form a recess (228), and a recessed gate (230,232) is formed in the recess.

公开(公告)号：EP1804288A2

公开(公告)日：2007-07-04

申请号：EP06011519.3

申请日：2006-06-02

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10835 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10891

Abstract: A method for forming a semiconductor device is provided. The method comprises providing a substrate (100) with recessed gates (122) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions (104) of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions and the protrusions. Buried portions (134a,b) of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines (140) are formed across the recessed gates. Bit lines (150) are formed to electrically connect the buried bit line contacts (134a) without crossing the capacitor buried surface straps (134b), and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.

Abstract translation: 提供了一种用于形成半导体器件的方法。 该方法包括提供具有凹陷栅极（122）和深沟槽电容器装置（102），其中的基片（100）。 凹入栅极与深沟槽电容器的装置的上部（104）的突起（120）显露。 间隔物（124）形成在所述上部分和所述突出的侧壁。 掩埋部分（134A，B）导电性材料形成在间隔件之间的空间。 基板，间隔物和掩埋部分被图案化，以形成平行的浅沟槽用于限定掩埋位线触点和电容器掩埋表面带。 介电材料的层中的浅沟槽形成。 字线（140）在各个凹门形成。 位线（150）形成电连接到掩埋位线接点（134A），而不跨越电容器掩埋表面带（134B），和堆叠电容形成电与电容器掩埋表面带连接。 因此，一个半导体装置。

公开(公告)号：EP3550567A1

公开(公告)日：2019-10-09

申请号：EP18202567.6

申请日：2018-10-25

Applicant: Nanya Technology Corporation

Inventor： Chang, Chuan-Jen ,  Lee, Wen-Ming

IPC: G11C7/10 ,  G11C7/22 ,  H03L7/085

Abstract: A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

公开(公告)号：EP2490222B1

公开(公告)日：2017-01-11

申请号：EP12155499.2

申请日：2012-02-15

Applicant: Nanya Technology Corporation

Inventor： Ting, Tah-Kang Joseph

IPC: G11C11/405 ,  G11C7/02 ,  G11C11/4097 ,  G11C7/18

CPC classification number: G11C11/405 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory cell (100) having a first switch device (Tr1), a second switch device (Tr2) and a capacitor (C) is disclosed. The first switch device (Tr1) has a control terminal coupled to and controlled by a select line (SL), a first terminal coupled to a bit line (BL), and a second terminal. The second switch device (Tr2) has a first terminal coupled to the second terminal of the first switch device (Tr1), a control terminal coupled to and controlled by a word line (WL), and a second terminal. The capacitor (C) has a first terminal coupled to the second terminal of the second switch device (Tr2) and a second terminal coupled to a predetermined voltage level, wherein data is read from the capacitor (C) or written to the capacitor (C) via the bit line (BL).

公开(公告)号：EP2490222A1

公开(公告)日：2012-08-22

申请号：EP12155499.2

申请日：2012-02-15

Applicant: Nanya Technology Corporation

Inventor： Ting, Tah-Kang Joseph

IPC: G11C11/405 ,  G11C7/02 ,  G11C11/4097 ,  G11C7/18

CPC classification number: G11C11/405 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097

Abstract: A memory cell (100) having a first switch device (Tr1), a second switch device (Tr2) and a capacitor (C) is disclosed. The first switch device (Tr1) has a control terminal coupled to and controlled by a select line (SL), a first terminal coupled to a bit line (BL), and a second terminal. The second switch device (Tr2) has a first terminal coupled to the second terminal of the first switch device (Tr1), a control terminal coupled to and controlled by a word line (WL), and a second terminal. The capacitor (C) has a first terminal coupled to the second terminal of the second switch device (Tr2) and a second terminal coupled to a predetermined voltage level, wherein data is read from the capacitor (C) or written to the capacitor (C) via the bit line (BL).

Abstract translation: 公开了具有第一开关器件（Tr1），第二开关器件（Tr2）和电容器（C）的存储器单元（100）。 第一开关器件（Tr1）具有耦合到选择线（SL）并由其控制的控制端子，耦合到位线（BL）的第一端子以及第二端子。 第二开关器件（Tr2）具有耦合到第一开关器件（Tr1）的第二端子的第一端子，耦合到字线（WL）并由字线（WL）控制的控制端子以及第二端子。 电容器（C）具有耦合到第二开关器件（Tr2）的第二端子的第一端子和耦合到预定电压电平的第二端子，其中数据从电容器（C）读取或写入到电容器（C ）通过位线（BL）。

公开(公告)号：EP1953842A3

公开(公告)日：2010-03-10

申请号：EP07024442.1

申请日：2007-12-17

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE ,  Powerchip Semiconductor Corp. ,  Nanya Technology Corporation ,  ProMOS Technologies, Inc. ,  WINBOND ELECTRONICS CORPORATION

Inventor： Hsu, Hong-Hui

IPC: H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

Abstract: A phase change memory device and fabrication method thereof is provided. The phase change memory device includes a substrate (300). A metal plug (304) is disposed on the substrate and a phase change material film (306a) is disposed on the metal plug, wherein the metal plug is electrically connected to the phase change material film. A heating electrode (312), preferably ring-shaped, is disposed on the phase change material film, wherein the heating electrode is electrically connected to the phase change material film. A conductive layer (316) is disposed on the heating electrode.

公开(公告)号：EP1804288A3

公开(公告)日：2009-04-15

申请号：EP06011519.3

申请日：2006-06-02

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10835 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10891

Abstract: A method for forming a semiconductor device is provided. The method comprises providing a substrate (100) with recessed gates (122) and deep trench capacitor devices (102) therein. Protrusions (120) of the recessed gates and upper portions (104) of the deep trench capacitor devices are revealed. Spacers (124) are formed on sidewalls of the upper portions and the protrusions. Buried portions (134a,b) of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines (140) are formed across the recessed gates. Bit lines (150) are formed to electrically connect the buried bit line contacts (134a) without crossing the capacitor buried surface straps (134b), and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.

公开(公告)号：EP1729338A2

公开(公告)日：2006-12-06

申请号：EP06010091.4

申请日：2006-05-16

Applicant: Nanya Technology Corporation

Inventor： Lee, Pei-Ing

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10891

Abstract: Method for forming a semiconductor memory device with a recessed gate. A substrate (208), having a plurality of deep trench capacitors (206) therein, is provided wherein upper portions of the deep trench capacitor devices are revealed. Spacers (226) on sidewalls of the upper portions of the deep trench capacitors are formed to form a predetermined region surrounded by the deep trench capacitor devices. The predetermined region of the substrate is etched using the spacers and the upper portions of the deep trench capacitors serve as a mask to form a recess (228), and a recessed gate (230,232) is formed in the recess.

Abstract translation: 用于形成具有凹入栅极的半导体存储器件的方法。 提供了其中具有多个深沟槽电容器（206）的衬底（208），其中露出了深沟槽电容器器件的上部。 深沟槽电容器的上部的侧壁上的间隔物（226）被形成为由深沟槽电容器器件包围的预定区域。 使用间隔物蚀刻衬底的预定区域，并且深沟槽电容器的上部用作掩模以形成凹部（228），并且在凹部中形成凹入栅极（230,232）。

公开(公告)号：EP3588503A1

公开(公告)日：2020-01-01

申请号：EP18208225.5

申请日：2018-11-26

Applicant: Nanya Technology Corporation

Inventor： LEE, Wen-Ming ,  CHANG, Chuan-Jen

IPC: G11C11/406

Abstract: A memory apparatus (100) and an operating method thereof are provided. The memory apparatus (100) includes a memory (110), a temperature sensor (120) and a control circuit (130). The temperature sensor (120) senses a temperature (TC) of the memory (110) and generating a temperature sensing signal (ST). The control circuit (130) is coupled to the memory (110) and the temperature sensor (120). The control circuit (130) performs access operation on the memory (110) and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal (ST).