公开(公告)号：WO2008002813A2

公开(公告)日：2008-01-03

申请号：PCT/US2007/071710

申请日：2007-06-20

Applicant: GRANDIS, INC. ,  RENESAS TECHNOLOGY CORP. ,  CHEN, Eugene, Youjun ,  HUAI, Yiming ,  PANCHULA, Alex, Fischer ,  WANG, Lien-Chang ,  LUO, Xiao

Inventor： CHEN, Eugene, Youjun ,  HUAI, Yiming ,  PANCHULA, Alex, Fischer ,  WANG, Lien-Chang ,  LUO, Xiao

IPC: G11C11/15

CPC classification number: G11C11/16

Abstract: A method and system for providing a magnetic memory is described. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each magnetic element has free and pinned layer(s) and a dominant spacer. The magnetic memory is configured such that either the read current(s) flow from the free layer(s) to the dominant spacer if the maximum low resistance state read current divided by the minimum low resistance state write current is greater than the maximum high resistance state read current divided by the minimum high resistance state write current or the read current(s) flow from the dominant spacer to the free layer(s) if the maximum low resistance state read current divided by the minimum low resistance state write current is less than the maximum high resistance state read current divided by the minimum high resistance state write current.

Abstract translation: 描述了一种用于提供磁存储器的方法和系统。 磁存储器包括阵列中的磁存储单元，位线和源极线。 每个磁存储单元包括至少一个磁性元件。 磁性元件可以通过驱动通过磁性元件的写入电流来编程。 每个磁性元件具有自由和固定的层和主要间隔物。 如果最大低电阻状态读取电流除以最小低电阻状态写入电流除以最大高电阻，则磁存储器被配置为使得读取电流从自由层流向主要间隔物 如果最小低电阻状态读取电流除以最小低电阻状态写入电流，则状态读取电流除以最小高电阻状态写入电流或从主要间隔物到自由层的读取电流（s） 比最大高电阻状态读取电流除以最小高电阻状态写入电流。

公开(公告)号：EP1780660A3

公开(公告)日：2010-06-09

申请号：EP06022553.9

申请日：2006-10-27

Applicant: Renesas Technology Corp.

Inventor： Watanabe, Kazuki, c/o Hitachi Ltd.

IPC: G06K19/07 ,  H02M3/07

CPC classification number: G06K19/0723 ,  G06K19/0713

Abstract: A semiconductor integrated circuit (2), provided with a charge pump circuit (9) of low power consumption, maintains an output voltage (VOUT) thereof at a predetermined voltage level without causing current consumption to undergo intermittent variation, and a contactless electronic device (1) using the semiconductor integrated circuit (2). With respective charge pump circuit unit cells (15,19), charge current/discharge current is controlled according to the output voltage (VOUT) of the charge pump circuit (9). The charge pump circuit (9) can maintain the output voltage (VOUT) thereof at the predetermined voltage level without undergoing an intermittent action. The charge current and discharge current are supplied from power supply terminals (PA,PB) of a power supply circuit (3), current control is executed by a transistor, and a voltage outputted according to the output voltage (VOUT) of the charge pump circuit (9) is supplied to the gate of the transistor.

公开(公告)号：EP2053656A3

公开(公告)日：2010-05-05

申请号：EP08253481.9

申请日：2008-10-24

Applicant: Renesas Technology Corp.

Inventor： Okura, Yasutaka c/o Hitachi, Ltd., Int. Prop. Group, ,  Iwasaki, Tomio c/o Hitachi, Ltd., Int. Prop. Group, ,  Terasaki, Takeshi c/o Hitachi, Ltd., Int. Prop. Group,

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/78301 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01049 ,  H01L2924/01005

Abstract: A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead is provided. The plating film formed on the surface of the lead is formed so that a particular plane orientation among plane orientations of tin constituting the plating film is parallel to the surface of the lead. Specifically, the plating film is formed so that the (001) plane of tin is parallel to the surface of the lead. Thus, the coefficient of thermal expansion of tin constituting the plating film can be made to be lower than a coefficient of thermal expansion of the copper constituting the lead.

公开(公告)号：EP1939937A3

公开(公告)日：2010-03-03

申请号：EP07255056.9

申请日：2007-12-27

Applicant: Renesas Technology Corp.

Inventor： Osawa, Michitaka, c/o Hitachi Ld. I.P.Group ,  Kanazawa, Takamitsu, c/o Hitachi Ld. I.P.Group

IPC: H01L23/492 ,  H01L25/07

CPC classification number: H01L24/49 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.

公开(公告)号：EP2093793A2

公开(公告)日：2009-08-26

申请号：EP09250234.3

申请日：2009-01-28

Applicant: Renesas Technology Corp.

Inventor： Muto, Akira c/o Renesas Technology Corp., IP Property Div. ,  Koike, Nobuya c/o Renesas Technology Corp., IP Property Div. ,  Arai, Katsuo c/o Renesas Technology Corp., IP Property Div. ,  Fujiki, Atsushi c/o Renesas Technology Corp., IP Property Div.

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/433 ,  H01L23/4334 ,  H01L23/49537 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/33 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/83 ,  H01L25/115 ,  H01L25/117 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29499 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/40247 ,  H01L2224/4899 ,  H01L2224/73263 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83139 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83885 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2225/1029 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/07025 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/37599

Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surfaceof an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip. At the same time, paste-like bonding material and a film member are placed between the source terminal 3 and gate terminal and the semiconductor chip. The paste-like bonding material is cured and turned into bonding material. As the result of use of the film members, variation in the thickness of the bonding material is suppressed.

Abstract translation: 提高树脂密封半导体封装的放射性能，进一步提高其制造成品率。 耦合到半导体芯片的背表面漏电极的漏极端子在封装树脂部分的背面露出。 以下部分和端子的一部分暴露在封装树脂部分的顶表面处：耦合到半导体芯片的源极焊盘电极的源极端子的第一部分和耦合到半导体芯片的栅极焊盘电极的栅极端子 。 源极端子和栅极端子的第二部分的剩余部分在封装树脂部分的背面露出。 当制造该半导体器件时，将接合材料和膜部件置于漏极端子和半导体芯片之间。 同时，在源极端子3和栅极端子与半导体芯片之间放置糊状接合材料和膜部件。 糊状结合材料固化并变成粘结材料。 作为使用膜构件的结果，抑制了接合材料的厚度的变化。

公开(公告)号：EP1650698B1

公开(公告)日：2009-08-12

申请号：EP05023055.6

申请日：2005-10-21

Applicant: Sony Corporation ,  Renesas Technology Corp.

Inventor： Aoki, Yoshitaka ,  Bando, Hideaki ,  Tsutsui, Keiichi ,  Nishizawa, Hirotaka ,  Ohsawa, Kenji ,  Totsuka, Takashi

IPC: G06K19/077

CPC classification number: G06K19/07732 ,  G06K19/07735 ,  G06K19/07743 ,  G06K19/07769

公开(公告)号：EP1722484B1

公开(公告)日：2009-05-27

申请号：EP06017561.9

申请日：2000-11-15

Applicant: Renesas Technology Corp. ,  TTPCOM Limited

Inventor： Tanaka, Satoshi c/o Hitachi, Ltd. Intellectual Property Group ,  Watanabe, Kazuo c/o Hitachi, Ltd. Intellectual Property Group ,  Hotta, Masao c/o Hitachi, Ltd. Intellectual Property Group ,  Hongo,Toyohiko c/o Hitachi, Ltd. Intellectual Property Group ,  Yamawaki, Taizo c/o Hitachi, Ltd. Intellectual Property Group ,  Kasahara, Masumi c/o Hitachi, Ltd. Intellectual Property Group ,  Takikawa, Kumiko c/o Hitachi, Ltd. Intellectual Property Group

IPC: H04B1/30 ,  H03D3/00 ,  H03F1/30

CPC classification number: H04B1/30 ,  H03D2200/0047 ,  H03K21/16

公开(公告)号：EP2056509A2

公开(公告)日：2009-05-06

申请号：EP08167467.3

申请日：2008-10-24

Applicant: Renesas Technology Corp.

Inventor： Zhang, Jinyun ,  Peng, Fei

IPC: H04L1/00

CPC classification number: H04L1/002 ,  H04L1/0003 ,  H04L1/0009 ,  H04L1/0017 ,  H04L5/0046 ,  H04L5/0053 ,  H04L25/0204 ,  H04L25/022

Abstract: A multiple carrier wireless communications system includes a channel predictor, a performance predictor, and a link adapter. The channel predictor is configured to predict channel state information for a next packet based on channel state information for the current packet. The performance predictor includes an uncoded performance predictor configured to predict system performance at an input of a decoder based on a modulation type and the predicted channel state information for the next packet, and a decoder input-output performance mapper configured to determine a required coding rate based on a requested system performance and the predicted system performance at the input of the decoder. The link adapter includes a modulation and coding scheme (MCS) updater configured to identify a MCS based on the required coding rate.

Abstract translation: 多载波无线通信系统包括信道预测器，性能预测器和链路适配器。 信道预测器被配置为基于当前分组的信道状态信息来预测下一分组的信道状态信息。 性能预测器包括未编码的性能预测器，其被配置为基于调制类型和用于下一个分组的预测的信道状态信息来预测解码器输入端的系统性能;以及解码器输入 - 输出性能映射器，被配置为确定所需的编码率 基于所请求的系统性能和解码器输入端的预测系统性能。 链路适配器包括被配置为基于所需编码速率来识别MCS的调制和编码方案（MCS）更新器。

公开(公告)号：EP2040378A1

公开(公告)日：2009-03-25

申请号：EP06780693.5

申请日：2006-06-30

Applicant: Renesas Technology Corp.

Inventor： TAKAI, Kazuyoshi ,  YASHITA, Takahiro ,  KATO, Kikuo ,  KUBO, Kazuaki

IPC: H03K17/06

CPC classification number: H03K17/6874 ,  H02M3/07 ,  H02M2003/072 ,  H03K17/063 ,  H03K17/102 ,  H03K17/693 ,  Y10T307/625 ,  Y10T307/76

Abstract: In a power phase period when in normal operation, switch portions SW2H and SW2L and switch portions SW3H and SW3L are turned ON, respectively, and switch portions SW1H and SW1L are turned OFF. And floating power supply is provided from an electrostatic capacitance element CS to buses A and B, a floating control circuit 4, a transmitter circuit 5, and a receiver circuit 6, respectively. In a data phase period, the switch portions SW1H and SW1L are turned ON, and the switch portions SW2H, SW2L, SW3H, and SW3L are turned OFF. By that manner, the electrostatic capacitance element CS is charged by the power supply of a battery B, and an electrostatic capacitance element CH provides the floating power supply to the floating control circuit 4, the transmitter circuit 5, and the receiver circuit 6, respectively. By this manner, a floating switch unit 7 in which the number of the switch portions is considerably reduced can be configured.

Abstract translation: 在通常动作的电力相位期间，开关部SW2H，SW2L和开关部SW3H，SW3L分别导通，开关部SW1H，SW1L分别断开。 并且浮动电源分别从静电电容元件CS提供给总线A和B，浮动控制电路4，发送器电路5和接收器电路6。 在数据相位期间，开关部分SW1H和SW1L导通，开关部分SW2H，SW2L，SW3H和SW3L截止。 通过这种方式，静电电容元件CS由电池B的电源充电，静电电容元件CH分别向浮动控制电路4，发送器电路5和接收器电路6提供浮动电源 。 通过这种方式，可以构成开关部分的数量明显减少的浮动开关单元7。

公开(公告)号：EP2005476A2

公开(公告)日：2008-12-24

申请号：EP07754687.7

申请日：2007-03-29

Applicant: Grandis, Inc. ,  Renesas Technology Corp.

Inventor： WANG, Lien-Chang ,  CHEN, Eugene Youjun ,  HUAI, Yiming ,  DIAO, Zhitao

IPC: H01L29/74

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12

Abstract: Techniques and device designs associated with devices having magnetic or magnetoresistive tunnel junctions (MTJs) configured to operate based on spin torque transfer switching. On-plug MTJ designs and fabrication techniques are described.