公开(公告)号：WO2012118577A1

公开(公告)日：2012-09-07

申请号：PCT/US2012/022708

申请日：2012-01-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GUNAWAN, Oki ,  KIM, Jeehwan ,  MITZI, David, B. ,  SADANA, Devendra, K. ,  TODOROV, Teodor, K.

Inventor： GUNAWAN, Oki ,  KIM, Jeehwan ,  MITZI, David, B. ,  SADANA, Devendra, K. ,  TODOROV, Teodor, K.

IPC: H01L31/0256

CPC classification number: H01L31/0326 ,  C23C14/34 ,  C25D7/12 ,  H01L31/076 ,  H01L31/078 ,  H01L31/18 ,  H01L31/20 ,  Y02E10/548

Abstract: A photosensitive device and method includes a top cell (102) having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell (104) includes an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. The bottom intrinsic layer includes a Cu-Zn-Sn containing chalcogenide (116).

Abstract translation: 感光装置和方法包括具有N型层的顶层单元（102），P型层和其间的顶层本征层。 底部单元（104）包括N型层，P型层和底层本征层。 底部本征层包括含有Cu-Zn-Sn的硫族化物（116）。

公开(公告)号：WO2006003061A1

公开(公告)日：2006-01-12

申请号：PCT/EP2005/052424

申请日：2005-05-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Compagnie IBM France ,  ADAM, Thomas, N ,  BEDELL, Stephen, W. ,  DE SOUZA, Joel, P. ,  FOGEL, Keith, E. ,  REZNICEK, Alexander ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam

Inventor： ADAM, Thomas, N ,  BEDELL, Stephen, W. ,  DE SOUZA, Joel, P. ,  FOGEL, Keith, E. ,  REZNICEK, Alexander ,  SADANA, Devendra, K. ,  SHAHIDI, Ghavam

IPC: H01L21/762

CPC classification number: H01L21/76259 ,  Y10S438/967

Abstract: A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

Abstract translation: 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：WO2005031810A3

公开(公告)日：2005-06-23

申请号：PCT/US2004029378

申请日：2004-09-10

Applicant: IBM ,  BEDELL STEPHEN W ,  CHOE KWANG SU ,  FOGEL KEITH F ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHOE KWANG SU ,  FOGEL KEITH F ,  SADANA DEVENDRA K

IPC: C22F1/10 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76227 ,  C22F1/10 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/76245 ,  H01L29/78603

Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

Abstract translation: 提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。 该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

公开(公告)号：WO2005034209A2

公开(公告)日：2005-04-14

申请号：PCT/US2004/031823

申请日：2004-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES ,  CHOE, Kwang, Su ,  FOGEL, Keith, E. ,  MAURER, Siegfried, L. ,  MITCHELL, Ryan, M. ,  SADANA, Devendra, K.

Inventor： CHOE, Kwang, Su ,  FOGEL, Keith, E. ,  MAURER, Siegfried, L. ,  MITCHELL, Ryan, M. ,  SADANA, Devendra, K.

IPC: H01L21/00

CPC classification number: H01L21/76243 ,  H01L21/26533 ,  H01L21/3063 ,  H01L21/31662

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract translation: 提供了一种制造在含Si覆盖层之下具有薄但均匀的掩埋氧化物区的绝缘体上硅（SOI）的方法。 通过首先改变含Si衬底的表面以包含大量空位或空隙来制造SOI结构。 接下来，通常但不总是在衬底上形成含Si层，然后利用低氧剂量将氧离子注入到结构中。 然后对结构进行退火以将注入的氧离子转换成薄但均匀的热埋氧化物区域。

公开(公告)号：WO2005031810A2

公开(公告)日：2005-04-07

申请号：PCT/US2004/029378

申请日：2004-09-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BEDELL, Stephen, W. ,  CHOE, Kwang, Su ,  FOGEL, Keith, F. ,  SADANA, Devendra, K.

Inventor： BEDELL, Stephen, W. ,  CHOE, Kwang, Su ,  FOGEL, Keith, F. ,  SADANA, Devendra, K.

IPC: H01L21/00

CPC classification number: H01L21/76227 ,  C22F1/10 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/76245 ,  H01L29/78603

Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

Abstract translation: 提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。 该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

公开(公告)号：WO2013012454A1

公开(公告)日：2013-01-24

申请号：PCT/US2012/028686

申请日：2012-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HEKMATSHOAR-TABARI, Bahman ,  HOPSTAKEN, Marinus ,  PARK, Dae-Gyu ,  SADANA, Devendra K. ,  SHAHIDI, Ghavam G. ,  SHAHRJERDI, Davood

Inventor： HEKMATSHOAR-TABARI, Bahman ,  HOPSTAKEN, Marinus ,  PARK, Dae-Gyu ,  SADANA, Devendra K. ,  SHAHIDI, Ghavam G. ,  SHAHRJERDI, Davood

IPC: H01L21/265

CPC classification number: H01L31/03762 ,  H01L31/02167 ,  H01L31/075 ,  H01L31/1864 ,  H01L31/202 ,  Y02E10/548 ,  Y02P70/521

Abstract: A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material.

Abstract translation: 一种形成光电器件的半导体材料的方法，该方法包括提供含氢化非晶硅的材料的表面，以及在含氘气氛中对含氢化非晶硅的材料进行退火。 来自含氘气体的氘通过含氢化非晶硅材料的表面被引入到含氢化非晶硅材料的晶格中。 在一些实施方案中，引入含氢可氢化非晶硅的晶格的晶格的氘增加了含氢化非晶硅的材料的稳定性。

公开(公告)号：WO2012177384A1

公开(公告)日：2012-12-27

申请号：PCT/US2012/040881

申请日：2012-06-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHANDRA, Bhupesh ,  HONG, Augustin, J. ,  KIM, Jeehwan ,  SADANA, Devendra, K. ,  TULEVSKI, George, S.

Inventor： CHANDRA, Bhupesh ,  HONG, Augustin, J. ,  KIM, Jeehwan ,  SADANA, Devendra, K. ,  TULEVSKI, George, S.

IPC: H01L31/00

CPC classification number: H01L31/022466 ,  B82Y30/00 ,  H01L31/075 ,  Y02E10/548

Abstract: A photovoltaic device and method include a photovoltaic stack having an N-doped layer (112), a P-doped layer (108) and an intrinsic layer (1 10). A transparent electrode (104) is formed on the photovoltaic stack and includes a carbon based layer (105) and a high work function metal layer (107). The high work function metal layer is disposed at an interface between the carbon based layer and the P-doped layer such that the high work function metal layer forms a reduced barrier contact and is light transmissive.

Abstract translation: 光伏器件和方法包括具有N掺杂层（112），P掺杂层（108）和本征层（110）的光伏堆栈。 透明电极（104）形成在光伏堆栈上，并包括碳基层（105）和高功函数金属层（107）。 高功函数金属层设置在碳基层和P掺杂层之间的界面处，使得高功函数金属层形成降低的屏障接触并且是透光的。

公开(公告)号：WO2012166298A1

公开(公告)日：2012-12-06

申请号：PCT/US2012/036860

申请日：2012-05-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY ,  KHAYYAT, Maha M. ,  SOSA CORTES, Norma E. ,  SAENGER, Katherine L. ,  BEDELL, Stephen W. ,  SADANA, Devendra K.

Inventor： KHAYYAT, Maha M. ,  SOSA CORTES, Norma E. ,  SAENGER, Katherine L. ,  BEDELL, Stephen W. ,  SADANA, Devendra K.

IPC: H01L21/30

CPC classification number: H01L21/187

Abstract: Method to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths are provided. In one embodiment, the method includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature. Next, the base substrate including the stressor layer is brought to a second temperature which is less than room temperature. The base substrate is spalled at the second temperature to form a spalled material layer. Thereafter, the spalled material layer is returned to room temperature, i.e., the first temperature.

Abstract translation: 方法：（i）对材料剥落过程引入额外的控制，从而改善裂纹的产生和传播，并提供（ii）提高选择性剥落深度的范围。 在一个实施例中，该方法包括在室温下的第一温度下在基底基板的表面上提供应力层。 接下来，包括应力层的基底衬底达到小于室温的第二温度。 基底基板在第二温度下剥离以形成剥离的材料层。 此后，剥离的材料层返回到室温，即第一温度。

公开(公告)号：WO2010080292A1

公开(公告)日：2010-07-15

申请号：PCT/US2009/067102

申请日：2009-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORP. ,  CHU, Jack O. ,  DENNARD, Robert H. ,  OTT, John A. ,  SADANA, Devendra K. ,  SHI, Leathen

Inventor： CHU, Jack O. ,  DENNARD, Robert H. ,  OTT, John A. ,  SADANA, Devendra K. ,  SHI, Leathen

IPC: H01L27/00

CPC classification number: H01L21/76254

Abstract: A semiconductor wafer structure for integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate; an electrically conductive layer formed on the lower insulating layer; an upper insulating layer formed on the electrically conductive layer, the upper insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; and a semiconductor layer formed on the upper insulating layer

Abstract translation: 用于集成电路器件的半导体晶片结构包括块状衬底; 形成在本体基板上的下绝缘层; 形成在下绝缘层上的导电层; 形成在所述导电层上的上绝缘层，所述上绝缘层由一对在其间具有接合界面的单独绝缘层形成; 以及形成在上绝缘层上的半导体层

公开(公告)号：WO2007149581A3

公开(公告)日：2008-08-28

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 一种含半导体的异质结构，包括从底部到顶部的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，载流子在特定栅极偏置范围内被限制在沟道层上。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。