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    Clock Generation
    18.
    发明公开
    Clock Generation 失效
    Takterzeugungsschaltung

    公开(公告)号：EP0803791A1

    公开(公告)日：1997-10-29

    申请号：EP97201653.9

    申请日：1990-06-26

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Buckingham, Keith ,  Simpson, Robert John

    IPC: G06F1/04 ,  G06F13/40 ,  H03M9/00

    CPC classification number: G06F1/04 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/151

    Abstract: Clock generation circuitry comprises: a plurality of sequentially connected delay devices (Do-D5), a first one of which is coupled to receive the first clock signal, each delay device being operable to produce a trigger signal and an output signal at a predetermined time after receiving a trigger signal from the previously connected delay device; control means (14) common to said delay devices for controlling said predetermined time interval; and output means (16) coupled to receive the output signals of the delay devices to produce therefrom said second clock signal.

    Abstract translation: 时钟生成电路包括：多个顺序连接的延迟装置（Do-D5），其中第一个延迟装置被耦合以接收第一时钟信号，每个延迟装置可操作以在预定时间产生触发信号和输出信号 在从先前连接的延迟装置接收到触发信号之后; 用于控制所述预定时间间隔的所述延迟装置共用的控制装置（14） 和输出装置（16），其耦合以接收延迟装置的输出信号，从而产生所述第二时钟信号。

    A circuit for generating an output signal having a 50% duty cycle
    19.
    发明公开
    A circuit for generating an output signal having a 50% duty cycle 失效
    Schaltungsanordnung zur Erzeugung eines Ausgangssignals mit 50％Tastverhältnis

    公开(公告)号：EP0772297A1

    公开(公告)日：1997-05-07

    申请号：EP96307757.3

    申请日：1996-10-25

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： Mellot, Pascal

    IPC: H03K5/156

    CPC classification number: H03K5/1565

    Abstract: The present invention concerns a circuit for generating an output signal that comprises an oscillator for providing a first control signal, the circuit further comprising: a reference generator that provides a first reference signal; control circuitry that is responsive to the first reference signal and a second reference signal for providing a second control signal; a first current source load inverter that is responsive to the second control signal for providing the second reference signal; and circuitry for providing the output signal that has a duty cycle substantially equal to 50% and which has a frequency substantially equal to f.

    Abstract translation: 本发明涉及一种用于产生包括用于提供第一控制信号的振荡器的输出信号的电路，该电路还包括：提供第一参考信号的参考发生器; 响应于第一参考信号的控制电路和用于提供第二控制信号的第二参考信号; 第一电流源负载逆变器，响应于所述第二控制信号提供所述第二参考信号; 以及用于提供具有基本上等于50％的占空比并且具有基本上等于f的频率的输出信号的电路。

    A satellite tuner stage
    20.
    发明公开
    A satellite tuner stage 失效
    TunerstufefürSatelliten

    公开(公告)号：EP0715403A1

    公开(公告)日：1996-06-05

    申请号：EP95308604.8

    申请日：1995-11-29

    Applicant: SGS-Thomson Microelectronics Limited

    Inventor： James, John C.

    IPC: H03D7/16

    CPC classification number: H03D7/165

    Abstract: A tuner stage of a satellite receiver system, receiving a signal from a low noise block for selecting a required channel carrier frequency, that comprises: an oscillator (20) for providing output signals at a selected frequency that have a 90° phase difference; first and second mixers (18a,18b) for mixing the signal from the low noise block with the signals from the oscillator (20); a means (22) for introducing a further 90° phase shift between the output signals of the mixer (18a,18b) at a required frequency that is equal to the difference between the selected frequency and the required channel carrier frequency; a first switchable summer (24) for summing the signals from said means; and a filter (26), whose centre frequency equals the required frequency, for filtering the summed signals.

    Abstract translation: 卫星接收机系统的调谐器级，从低噪声块接收用于选择所需信道载波频率的信号，其包括：振荡器（20），用于提供具有90°相位差的选定频率的输出信号; 用于将来自低噪声块的信号与来自振荡器（20）的信号混合的第一和第二混频器（18a，18b）; 用于在混频器（18a，18b）的输出信号之间以等于所选频率与所需信道载频之间的差的所需频率引入另外的90°相移的装置（22） 用于对来自所述装置的信号求和的第一可切换夏季（24） 以及滤波器（26），其中心频率等于所需频率，用于对相加的信号进行滤波。

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