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    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS
    12.
    发明申请
    PROTECTION AGAINST CHARGING DAMAGE IN HYBRID ORIENTATION TRANSISTORS 审中-公开
    在混合方向晶体管中对充电损害的保护

    公开(公告)号：WO2007115146B1

    公开(公告)日：2008-06-05

    申请号：PCT/US2007065604

    申请日：2007-03-30

    Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

    IPC: H02H9/00

    CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下面的体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）通过埋入介质层（16）设置在与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

    INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE
    13.
    发明申请
    INTEGRATED SEMICONDUCTOR DEVICES WITH SINGLE CRYSTALLINE BEAM, METHODS OF MANUFACTURE AND DESIGN STRUCTURE 审中-公开
    具有单晶光束的集成半导体器件，制造方法和设计结构

    公开(公告)号：WO2013070294A1

    公开(公告)日：2013-05-16

    申请号：PCT/US2012/050743

    申请日：2012-08-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  HARAME, David, L. ,  STAMPER, Anthony, K.

    Inventor： HARAME, David, L. ,  STAMPER, Anthony, K.

    IPC: H03H9/54

    CPC classification number: B81B3/0027 ,  B81B2201/0285 ,  H01L21/84 ,  H01L27/1203 ,  H01L41/1136 ,  H01L2224/73265 ,  H03H3/02 ,  H03H9/1007 ,  H03H9/173 ,  H03H2001/0064 ,  H03H2003/027 ,  H03H2009/155 ,  H03H2009/241

    Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam (18) from a silicon layer (14) on an insulator (12). The method further includes providing a coating of insulator material (22) over the single crystalline beam. The method further includes forming a via (34a) through the insulator material exposing a wafer (10) underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material (36) in the via and over the insulator material. The method further includes providing a lid (38) on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity (42a) above the single crystalline beam and a lower cavity (42b) in the wafer, below the single crystalline beam.

    Abstract translation: 提供了与CMOS器件集成的体声波滤波器和/或体声波谐振器，制造方法和设计结构。 该方法包括从绝缘体（12）上的硅层（14）形成单晶束（18）。 该方法还包括在单晶束上提供绝缘体材料（22）的涂层。 该方法还包括通过暴露出绝缘体下方的晶片（10）的绝缘体材料形成通孔（34a）。 绝缘体材料保留在单晶束上。 该方法还包括在通孔和绝缘体材料上提供牺牲材料（36）。 该方法还包括在牺牲材料上提供盖（38）。 该方法还包括在单结晶体束下通过盖子将牺牲材料和晶片的一部分排出，以在晶片上方形成上空腔（42a），并在晶片的下方形成下空腔（42b） 单晶束。

    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
    18.
    发明申请
    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 审中-公开
    通过VIAS的低电阻和电感及其制造方法

    公开(公告)号：WO2007084879A2

    公开(公告)日：2007-07-26

    申请号：PCT/US2007/060544

    申请日：2007-01-15

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ERTURK, Mete ,  GROVES, Robert, A. ,  JOHNSON, Jeffrey, B. ,  JOSEPH, Alvin, J. ,  LIU, Qizhi ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K.

    Inventor： ERTURK, Mete ,  GROVES, Robert, A. ,  JOHNSON, Jeffrey, B. ,  JOSEPH, Alvin, J. ,  LIU, Qizhi ,  SPROGIS, Edmund, J. ,  STAMPER, Anthony, K.

    IPC: H01L21/50

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation (250) in a substrate (100), the substrate (100) having a frontside and an opposing backside; forming a first dielectric layer (105) on the frontside of the substrate (100); forming a trench (265C) in the first dielectric layer (105), the trench (265C) aligned over and within a perimeter of the dielectric isolation (250) and extending to the dielectric isolation (250); extending the trench (265C) formed in the first dielectric layer (1 05) through the dielectric isolation (250) and into the substrate (1 00)to a depth (Dl ) less than a thickness of the substrate (1 00); filling the trench (265C) and co-planarizing a top surface of the trench (265C) with a top surface of the first dielectric layer (1 05) to form an electrically conductive through via (270C); and thinning the substrate (100) from a backside of the substrate (100) to expose the through via (270C).

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底（100）中形成绝缘隔离（250），所述衬底（100）具有前侧和相对的背面; 在所述基板（100）的前侧形成第一电介质层（105）; 在所述第一电介质层（105）中形成沟槽（265C），所述沟槽（265C）在所述介电隔离（250）的周边内并且在所述介质隔离（250）的周边内对准并且延伸到所述电介质隔离（250）; 将形成在第一电介质层（105）中的沟槽（265C）延伸通过电介质隔离（250）并延伸到衬底（100）中至达到小于衬底厚度（001）的深度（D1）。 填充沟槽（265C）并且将沟槽（265C）的顶表面与第一介电层（105）的顶表面共平化以形成导电通孔（270C）; 以及从所述衬底（100）的背面使所述衬底（100）变薄以暴露所述通孔（270C）。

    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES
    20.
    发明申请
    MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) AND RELATED ACTUATOR BUMPS, METHOD OF MANUFACTURE AND DESIGN STRUCTURES 审中-公开
    微电子机械系统（MEMS）及相关执行机构的制造，制造和设计结构的方法

    公开(公告)号：WO2012177304A3

    公开(公告)日：2014-03-13

    申请号：PCT/US2012029005

    申请日：2012-03-14

    Applicant: IBM ,  JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

    Inventor： JAHNES CHRISTOPHER V ,  STAMPER ANTHONY K

    IPC: B81B3/00

    CPC classification number: H01H59/0009 ,  B81B3/001 ,  B81B7/0006 ,  B81B2201/016 ,  B81B2203/0118 ,  B81B2203/04 ,  B81C1/0015 ,  B81C1/00293 ,  B81C2203/0145 ,  G06F17/5045 ,  G06F17/5068 ,  H01H1/0036 ,  H01H2001/0057 ,  Y10T29/49121

    Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are provided. The method of forming a MEMS structure includes forming fixed actuator electrodes (115) and a contact point on a substrate. The method further includes forming a MEMS beam (100) over the fixed actuator electrodes and the contact point. The method further includes forming an array of actuator electrodes (105') in alignment with portions of the fixed actuator electrodes, which are sized and dimensioned to prevent the MEMS beam from collapsing on the fixed actuator electrodes after repeating cycling. The array of actuator electrodes are formed in direct contact with at least one of an underside of the MEMS beam and a surface of the fixed actuator electrodes.

    Abstract translation: 提供微机电系统（MEMS）结构，制造方法和设计结构。 形成MEMS结构的方法包括在基板上形成固定的致动器电极（115）和接触点。 该方法还包括在固定的致动器电极和接触点上形成MEMS光束（100）。 该方法还包括形成与固定致动器电极的部分对准的致动器电极阵列（105'），其尺寸和尺寸被设计成防止MEMS梁在重复循环之后塌陷在固定的致动器电极上。 致动器电极的阵列形成为与MEMS光束的下侧和固定的致动器电极的表面中的至少一个直接接触。

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