公开(公告)号：WO2006033722A3

公开(公告)日：2006-03-30

申请号：PCT/US2005/028569

申请日：2005-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  ELIEZER, Oren, E. ,  CRUISE, Francis, P. ,  STASZEWSKI, Robert, B.

Inventor： ELIEZER, Oren, E. ,  CRUISE, Francis, P. ,  STASZEWSKI, Robert, B.

IPC: H04L27/00 ,  H04L25/03 ,  H04L27/20 ,  H03C3/00

Abstract: Apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The complex modulator (110) comprises an I switch array (120), Q switch array (112) and matching network (114). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I + jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

公开(公告)号：WO2006033722A2

公开(公告)日：2006-03-30

申请号：PCT/US2005028569

申请日：2005-08-12

Applicant: TEXAS INSTRUMENTS INC ,  ELIEZER OREN E ,  CRUISE FRANCIS P ,  STASZEWSKI ROBERT B

Inventor： ELIEZER OREN E ,  CRUISE FRANCIS P ,  STASZEWSKI ROBERT B

IPC: H04K1/02

CPC classification number: H03F3/24 ,  H03C3/40 ,  H03C5/00 ,  H03F2200/324 ,  H03F2200/331 ,  H03F2200/336 ,  H04K1/02 ,  H04L27/04 ,  H04L27/2092 ,  H04L27/365

Abstract: Apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, ?). The complex modulator (110) comprises an I switch array (120), Q switch array (112) and matching network (114). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I + jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.

Abstract translation: 用于复数调制器的全数字正交架构的装置和方法。 复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标结构（r，θ）的结构。 复调制器（110）包括I开关阵列（120），Q开关阵列（112）和匹配网络（114）。 调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号 。 相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。 提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。

公开(公告)号：WO2005086759A2

公开(公告)日：2005-09-22

申请号：PCT/US2005/007326

申请日：2005-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  STASZEWSKI, Robert, B. ,  LEIPOLD, Dirk

Inventor： STASZEWSKI, Robert, B. ,  LEIPOLD, Dirk

IPC: H04L27/04

CPC classification number: H03J7/047 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03L1/00 ,  H03L2207/50

Abstract: A mobile device includes frequency synthesizer circuitry (44) for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator (72), without frequency stabilization circuitry. Variations in the output of the crystal oscillator (72) are compensated by adjusting the multiplication factor of the frequency synthesizer.

Abstract translation: 移动设备包括用于以参考频率的倍数产生频道频率的频率合成器电路（44）。 参考频率由自由运行的晶体振荡器（72）产生，没有频率稳定电路。 通过调整频率合成器的乘法因子来补偿晶体振荡器（72）的输出的变化。

公开(公告)号：WO2016119824A8

公开(公告)日：2017-08-24

申请号：PCT/EP2015051574

申请日：2015-01-27

Applicant: HUAWEI TECH CO LTD ,  SHAHMOHAMMADI MINA ,  BABAIE MASOUD ,  STASZEWSKI ROBERT

Inventor： SHAHMOHAMMADI MINA ,  BABAIE MASOUD ,  STASZEWSKI ROBERT

IPC: H03B5/12

CPC classification number: H03B5/1243 ,  H03B5/1218 ,  H03B5/1228 ,  H03B5/1262 ,  H03B5/1296 ,  H03B2201/0266

Abstract: The invention relates to a radio frequency oscillator (100), the radio frequency oscillator (100) comprising a resonator circuit (101) being resonant at an excitation of the resonator circuit (101) in a differential mode and at an excitation of the resonator circuit (101) in a common mode, wherein the resonator circuit (101) has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit (101) has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit (103) being configured to excite the resonator circuit (101) in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit (105) being configured to excite the resonator circuit (101) in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

Abstract translation: 本发明涉及射频振荡器（100），射频振荡器（100）包括谐振器电路（101），谐振器电路在谐振器电路（101）的激励下以差模和激励谐振器电路 （101），其中所述谐振器电路（101）在所述差模中的激励时具有差模谐振频率，并且其中所述谐振器电路（101）在所述共模中的激励处具有共模谐振频率 ，第一激励电路（103）被配置为在差模模式下激励谐振器电路（101）以获得在差模谐振频率下振荡的差模振荡器信号，第二激励电路（105）被配置为激励 谐振器电路（101），以获得以共模谐振频率振荡的共模振荡器信号。

公开(公告)号：WO2016124226A1

公开(公告)日：2016-08-11

申请号：PCT/EP2015/052183

申请日：2015-02-03

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

IPC: G04F10/00 ,  H03M1/50

CPC classification number: G04F10/005 ,  H03M3/414

Abstract: A time-to-digital converter (300, 400) includes: an input (302, 402) for receiving a time domain input signal (Tin); an output (306, 406) for providing a digital output signal (Dout); a time register (305, 405) coupled to the input (302, 403) and to a first node (308, 408); a time quantizer (307, 407) coupled to the time register (305, 405) for providing the digital output signal (Dout) at the output (306, 406); and a digital-to-time converter (309, 409) coupled to the output (306, 406) for providing a feed-back signal (E, Q err ) at the first node (308, 408).

Abstract translation: 时间数字转换器（300,400）包括：用于接收时域输入信号（Tin）的输入端（302,402）; 用于提供数字输出信号（Dout）的输出（306,406）; 耦合到输入（302,403）和第一节点（308,408）的时间寄存器（305,405）; 耦合到时间寄存器（305,405）的时间量化器（307,407），用于在输出端（306,406）处提供数字输出信号（Dout）; 以及耦合到所述输出（306,406）的数字 - 时间转换器（309,409），用于在所述第一节点（308,408）处提供反馈信号（E，Qerr）。

公开(公告)号：WO2014124690A1

公开(公告)日：2014-08-21

申请号：PCT/EP2013/053108

申请日：2013-02-15

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  STASZEWSKI, Robert Bogdan ,  BABAIE, Masoud ,  VISWESWARAN, Akshay ,  HE, Zhuobiao

Inventor： STASZEWSKI, Robert Bogdan ,  BABAIE, Masoud ,  VISWESWARAN, Akshay ,  HE, Zhuobiao

IPC: H03B5/12

CPC classification number: H03L7/06 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1296 ,  H03B2200/0036 ,  H03B2200/0048 ,  H03B2200/0062 ,  H03B2200/007 ,  H03B2200/0082 ,  H03H11/0405

Abstract: The invention relates to an oscillator(300), comprising: a pair of transistors (301, 303) which source terminals (SOURCEA, SOURCEB) are interconnected and which drain (DRAINA, DRAINB) and gate (GATEA, GATEB) terminals are coupled by a positive feedback loop comprising an oscillator tank (309), wherein the source terminals (SOURCEA, SOURCEB) of the transistors (301, 303) are connected to a current source (305) configured to control physical parameters of the oscillator(300).

Abstract translation: 本发明涉及一种振荡器（300），包括：源极端子（SOURCEA，SOURCEB）互连的一对晶体管（301,303），以及哪个漏极（DRAINA，DRAINB）和栅极（GATEA，GATEB）端子通过 包括振荡器箱（309）的正反馈回路，其中晶体管（301,303）的源极端子（SOURCEA，SOURCEB）连接到被配置为控制振荡器（300）的物理参数的电流源（305）。

公开(公告)号：WO2013189548A1

公开(公告)日：2013-12-27

申请号：PCT/EP2012/062030

申请日：2012-06-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  TOHIDIAN, Massoud ,  MADADI, Iman ,  STASZEWSKI, Robert Bogdan

Inventor： TOHIDIAN, Massoud ,  MADADI, Iman ,  STASZEWSKI, Robert Bogdan

IPC: H04B1/00

CPC classification number: H03D7/14 ,  H04B1/0003

Abstract: The invention relates to a radio frequency receiver (100) for receiving an analogue radio frequency signal (102), the radio frequency receiver (100) comprising: a sampling mixer (101) being configured to sample the analogue radio frequency signal (102) using a predetermined sampling rate (f s ) to obtain a discrete-time signal (104), and to shift the discrete-time signal (104) towards an intermediate frequency (106) to obtain an intermediate discrete-time signal (108) sampled at the predetermined sampling rate (f s ); and a processing circuit (103) for discrete-time processing the intermediate discrete-time signal (108) at the predetermined sampling rate (f s ).

Abstract translation: 本发明涉及一种用于接收模拟射频信号（102）的射频接收机（100），该射频接收机（100）包括：采样混频器（101），被配置为采用模拟射频信号（102） 以获得离散时间信号（104）的预定采样速率（fs），并且将离散时间信号（104）朝向中间频率（106）移位以获得在该时间信号（104）处采样的中间离散时间信号（108） 预定采样率（fs）; 以及用于以预定采样率（fs）对中间离散时间信号（108）进行离散时间处理的处理电路（103）。

公开(公告)号：WO2013091708A1

公开(公告)日：2013-06-27

申请号：PCT/EP2011/073823

申请日：2011-12-22

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  VISWESWARAN, Akshay ,  STASZEWSKI, Robert Bogdan ,  LONG, John

Inventor： VISWESWARAN, Akshay ,  STASZEWSKI, Robert Bogdan ,  LONG, John

IPC: H03B1/00

CPC classification number: H03B5/12 ,  H03B5/1218 ,  H03B5/1228 ,  H03B5/1265 ,  H03B5/1296

Abstract: The invention relates to an oscillator circuit (100), comprising a clipping element (101) for generating a clipped signal (121), and a first amplification stage (103) for amplifying and filtering the clipped signal (121) to obtain a filtered signal (123), wherein the clipping element (101) is configured to generate the clipped signal (121) upon the basis of the filtered signal.

Abstract translation: 本发明涉及一种振荡器电路（100），包括用于产生限幅信号（121）的限幅元件（101）和用于放大和滤波限幅信号（121）以获得滤波信号的第一放大级（103） （123），其中所述限幅元件（101）被配置为基于所述经滤波的信号来产生所述限幅信号（121）。

公开(公告)号：WO2013034771A3

公开(公告)日：2013-05-02

申请号：PCT/EP2012067673

申请日：2012-09-10

Applicant: BOROWSKI ANDRE ,  UNIV DELFT TECH ,  KUMAR PRIYANKA ,  STASZEWSKI ROBERT ,  CHARBON EDOARDO

Inventor： KUMAR PRIYANKA ,  STASZEWSKI ROBERT ,  CHARBON EDOARDO

IPC: G04F10/00 ,  G01T1/164 ,  G01T1/24

CPC classification number: H03M1/002 ,  G01B11/24 ,  G01T1/1647 ,  G04F10/005 ,  H04N5/378 ,  H04N13/02 ,  H04N2213/001

Abstract: 3D imager comprising at least one pixel, each pixel comprising a photodetector for detecting photon incidence and a time-to-digital converter system configured for referencing said photon incidence to a reference clock, the 3D imager further comprising a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for automatically adjusting the frequency of the reference clock on the basis of a time up to a subsequent photon incidence as estimated in a first series of measurements.

Abstract translation: 3D成像器包括至少一个像素，每个像素包括用于检测光子入射的光电检测器，以及配置用于将所述光子入射参考到参考时钟的时间 - 数字转换器系统，所述3D成像器还包括参考时钟发生器， 参考时钟，其中所述参考时钟发生器被配置为基于在第一系列测量中估计的直到随后的光子入射的时间自动调整所述参考时钟的频率。

公开(公告)号：WO2013034771A2

公开(公告)日：2013-03-14

申请号：PCT/EP2012/067673

申请日：2012-09-10

Applicant: BOROWSKI, André ,  TECHNISCHE UNIVERSITEIT DELFT ,  KUMAR, Priyanka ,  STASZEWSKI, Robert ,  CHARBON, Edoardo

Inventor： KUMAR, Priyanka ,  STASZEWSKI, Robert ,  CHARBON, Edoardo

CPC classification number: H03M1/002 ,  G01B11/24 ,  G01T1/1647 ,  G04F10/005 ,  H04N5/378 ,  H04N13/20 ,  H04N2213/001

Abstract: 3D imager comprising at least one pixel, each pixel comprising a photodetectorfor detecting photon incidence and a time-to-digital converter system configured for referencing said photon incidence to a reference clock, and further comprising a reference clock generator provided for generating the reference clock, wherein the reference clock generator is configured for adjusting the frequency of the reference clock on the basis of an estimated time up to a subsequent photon incidence

Abstract translation: 3D成像器包括至少一个像素，每个像素包括用于检测光子入射的光电检测器，以及配置用于将所述光子入射参考到参考时钟的时间 - 数字转换器系统，并且还包括用于产生参考时钟的参考时钟发生器， 其中所述参考时钟发生器被配置为基于直到随后的光子入射的估计时间来调整所述参考时钟的频率