公开(公告)号：WO2016119823A1

公开(公告)日：2016-08-04

申请号：PCT/EP2015/051573

申请日：2015-01-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  SHAHMOHAMMADI, Mina ,  BABAIE, Masoud ,  STASZEWSKI, Robert

Inventor： SHAHMOHAMMADI, Mina ,  BABAIE, Masoud ,  STASZEWSKI, Robert

IPC: H03B5/12

CPC classification number: H03B5/1228 ,  H03B5/1218 ,  H03B5/1243 ,  H03B5/1262 ,  H03B5/1265 ,  H03B5/1296 ,  H03B2201/0266

Abstract: The invention relates to a resonator circuit (100), the resonator circuit (100) comprising a transformer (101) comprising a primary winding (103) and a secondary winding (105), wherein the primary winding (103) is inductively coupled with the secondary winding (105), a primary capacitor (107) being connected to the primary winding (103), the primary capacitor (107) and the primary winding (103) forming a primary circuit, and a secondary capacitor (109) being connected to the secondary winding (105), the secondary capacitor (109) and the secondary winding (105) forming a secondary circuit, wherein the resonator circuit (100) has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit (100) has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.

Abstract translation: 本发明涉及一种谐振器电路（100），所述谐振器电路（100）包括包括初级绕组（103）和次级绕组（105）的变压器（101），其中初级绕组（103）感应耦合 次级绕组（105），连接到初级绕组（103）的主电容器（107），形成初级电路的初级电容器（107）和初级绕组（103），以及二次电容器（109） 所述次级绕组（105），所述次级电容器（109）和所述次级绕组（105）形成次级电路，其中所述谐振器电路（100）在共模激励初级电路时具有共模谐振频率， 其中所述谐振器电路（100）在差分模式下在所述初级电路的激励时具有差模谐振频率，并且其中所述共模谐振频率与所述差模谐振频率不同。

公开(公告)号：WO2013189546A1

公开(公告)日：2013-12-27

申请号：PCT/EP2012/062027

申请日：2012-06-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  TOHIDIAN, Massoud ,  MADADI, Iman ,  STASZEWSKI, Robert Bogdan

Inventor： TOHIDIAN, Massoud ,  MADADI, Iman ,  STASZEWSKI, Robert Bogdan

IPC: H03H15/00 ,  H03D7/12

CPC classification number: H03H11/04 ,  H03D7/125 ,  H03D7/165 ,  H03D2200/006 ,  H03D2200/0074 ,  H03H15/023

Abstract: The invention relates to a discrete-time filter for filtering an input signal, the discrete-time filter comprising a switched capacitor network, the switched capacitor network comprising an input (102) and an output (104), a number of switched capacitor paths (101, 103, 105, 107) arranged in parallel between the input (102) and the output (104), each switched capacitor path (101, 103, 105, 107) comprising a capacitor, and a switch circuitry (121, 125, 127) for switching each capacitor at a different time instant for outputting a filtered input signal.

Abstract translation: 本发明涉及用于对输入信号进行滤波的离散时间滤波器，离散时间滤波器包括开关电容网络，开关电容网络包括输入（102）和输出（104），多个开关电容器路径 （102）和输出（104）并联布置的每个开关电容器路径（101,103,105,107）包括电容器，以及开关电路（121,125,107） 127），用于在不同的时刻切换每个电容器，以输出滤波的输入信号。

公开(公告)号：WO2013034770A3

公开(公告)日：2013-05-02

申请号：PCT/EP2012067672

申请日：2012-09-10

Applicant: BOROWSKI ANDRE ,  UNIV DELFT TECH ,  KUMAR PRIYANKA ,  STASZEWSKI ROBERT ,  CHARBON EDOARDO

Inventor： KUMAR PRIYANKA ,  STASZEWSKI ROBERT ,  CHARBON EDOARDO

IPC: G04F10/00 ,  G01T1/164

CPC classification number: H03M1/002 ,  G01B11/24 ,  G01T1/1647 ,  G04F10/005 ,  H04N5/378 ,  H04N13/02 ,  H04N2213/001

Abstract: Time-to-digital converter system comprising: an event detector configured for detecting an event and generating an event detection signal upon detection of the event;and a time-to-digital converter coupled or connectable to the event detector and comprising a fine resolution part configured for counting fine time intervals, organized such that the fine resolution part is activated in response to the event detection signal and deactivated in response to a reference clock. 3D imager comprising an array of pixels, with in each pixel such a time-to-digital converter system, and further comprising a reference clock generator.

Abstract translation: 时间到数字转换器系统，包括：事件检测器，被配置为在检测到事件时检测事件并产生事件检测信号;以及时间 - 数字转换器，其耦合或连接到事件检测器，并且包括精细分辨率部分 被配置为对精细时间间隔进行计数，被组织成使得精细分辨率部分响应于事件检测信号被激活并且响应于参考时钟被去激活。 3D成像器包括像素阵列，每个像素中的诸如时间 - 数字转换器系统，还包括参考时钟发生器。

公开(公告)号：WO2016034242A1

公开(公告)日：2016-03-10

申请号：PCT/EP2014/068892

申请日：2014-09-05

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  MADADI, Iman ,  TOHIDIAN, Massoud ,  STASZEWSKI, Robert Bogdan

Inventor： MADADI, Iman ,  TOHIDIAN, Massoud ,  STASZEWSKI, Robert Bogdan

IPC: H03H19/00 ,  H03H15/00

CPC classification number: H03H19/004 ,  H03H15/00 ,  H03H15/023

Abstract: A charge sharing filter (303) includes: a rotating capacitor (C R ); and a plurality of elementary filters (311, 312, 313), each elementary filter comprising: an elementary switch (φ,) coupled between a first node (A i ) of the respective elementary filter and a second node (B i ) of the respective elementary filter; and a history capacitor (C H ) coupled to the first node (A i ) of the respective elementary filter, wherein the second nodes (B i ) of the plurality of elementary filters are interconnected with the rotating capacitor (C R ) in one interconnecting node (B).

Abstract translation: 电荷共享滤波器（303）包括：旋转电容器（CR）; 以及多个基本滤波器（311,312,313），每个基本滤波器包括：耦合在各个基本滤波器的第一节点（Ai）和各个基本单元的第二节点（Bi）之间的基本开关（φ） 过滤; 以及耦合到各个基本滤波器的第一节点（Ai）的历史电容器（CH），其中多个基本滤波器中的第二节点（Bi）与一个互连节点（B）中的旋转电容器（CR）互连， 。

公开(公告)号：WO2013189547A1

公开(公告)日：2013-12-27

申请号：PCT/EP2012/062029

申请日：2012-06-21

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  TOHIDIAN, Massoud ,  MADADI, Iman ,  STASZEWSKI, Robert Bogdan

Inventor： TOHIDIAN, Massoud ,  MADADI, Iman ,  STASZEWSKI, Robert Bogdan

IPC: H04B1/00

CPC classification number: H04B1/26 ,  H04B1/0007

Abstract: The invention relates to a superheterodyne receiver (100), comprising: a sampling mixer (101) being configured to sample an analogue radio frequency signal (102) using a predetermined sampling rate (fs) to obtain a discrete-time sampled signal (104), and to shift the discrete-time sampled signal (104) towards a first intermediate frequency (|f RF -f LO |) to obtain an intermediate discrete-time signal (108) sampled at the predetermined sampling rate (fs); a discrete-time filter (103) being configured to filter the intermediate discrete-time signal (108) at the predetermined sampling rate (fs) to obtain a filtered signal (130); and a discrete-time mixer (109) being configured to shift the filtered signal (130) towards a second intermediate frequency (f IF ).

Abstract translation: 本发明涉及一种超外差接收机（100），包括：采样混频器（101），其被配置为使用预定采样率（fs）对模拟射频信号（102）进行采样以获得离散时间采样信号（104） 并且将离散时间采样信号（104）朝向第一中间频率（| fRF-fLO |）移位，以获得以预定采样率（fs）采样的中间离散时间信号（108）; 离散时间滤波器（103）被配置为以预定采样率（fs）对中间离散时间信号（108）进行滤波以获得滤波信号（130）; 和离散时间混合器（109）被配置为将经滤波的信号（130）朝向第二中频（fIF）移位。

公开(公告)号：WO2005104380A3

公开(公告)日：2007-02-01

申请号：PCT/US2005013000

申请日：2005-04-18

Applicant: TEXAS INSTRUMENTS INC ,  MUHAMMAD KHURRAM ,  STASZEWSKI ROBERT B ,  LEIPOLD DIRK

Inventor： MUHAMMAD KHURRAM ,  STASZEWSKI ROBERT B ,  LEIPOLD DIRK

IPC: H04B1/69 ,  H03D7/18 ,  H03H19/00 ,  H04B1/16 ,  H04B1/28

CPC classification number: H03D7/18 ,  H03H19/004 ,  H03H2007/0192

Abstract: Disclosed are methods, circuits and systems for image reject filtering in a multi-tap direct sampling mixer (MTDSM) of an IF or RF system. Disclosed is the use of rotating capacitors among the in-phase and quadrature branches of a signal processing system. The exchange of information among the branches of the I and Q channels is used in the implementation of a complex filter. Rotation of a switched capacitor C R between the I and Q channels of the circuit causes a sharing of the charge among the four paths, I+, I-, Q+, Q-, resulting in a direct sampling and a complex filtering arrangement (10). The preferred embodiment of the filter (10) shown can be seen to have four sub-circuits (12, 14, 16, 18), which may be understood as single-pole IIR filters. Embodiments using cascaded multiple stages of the complex filter to provide higher order complex filters are also disclosed.

Abstract translation: 公开了用于IF或RF系统的多抽头直接采样混频器（MTDSM）中的图像抑制滤波的方法，电路和系统。 公开了在信号处理系统的同相和正交分支中使用旋转电容器。 在I和Q通道的分支之间的信息交换用于实现复杂的过滤器。 电路的I和Q通道之间的开关电容C R R的旋转导致四个路径I +，I，Q +，Q-之间的电荷共享，导致直接采样和 复杂的滤波装置（10）。 可以看出所示滤波器（10）的优选实施例具有四个子电路（12,14,16,18），其可被理解为单极IIR滤波器。 还公开了使用复合滤波器的级联多级以提供更高阶复数滤波器的实施例。

公开(公告)号：WO2004034572A1

公开(公告)日：2004-04-22

申请号：PCT/US2003/031857

申请日：2003-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  MUHAMMAD, Khurram ,  STASZEWSKI, Robert, B. ,  FEYGIN, Gennady

Inventor： MUHAMMAD, Khurram ,  STASZEWSKI, Robert, B. ,  FEYGIN, Gennady

IPC: H03F1/26

CPC classification number: H03D7/125 ,  H04B1/1036

Abstract: When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer (800) with capacitor banks (811) and (812) that are controlled by a digital control unit (820) with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.

Abstract translation: 当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。 不同的抽取率导致不同的频率混叠成所需的频带。 具有由数字控制单元（820）控制的电容器组（811）和（812）的电流模式采样混频器（800）具有以不同抽取率对RF电流进行积分和抽取的能力，能够测量频率 频谱具有不同的抽取率。 然后分析测量的频谱以检测混叠到期望频带的干扰源的存在。 然后可以消除或避免干扰源。

公开(公告)号：WO2016124227A1

公开(公告)日：2016-08-11

申请号：PCT/EP2015/052187

申请日：2015-02-03

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

Inventor： WU, Ying ,  STASZEWSKI, Robert ,  MAO, Yihong

IPC: G04F10/00 ,  H03M1/50

CPC classification number: G04F10/005 ,  H03H19/004 ,  H03K5/135 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/50 ,  H03M2201/4233

Abstract: A time register (300) includes: a pair of inputs (345, 346) coupled to a pair of input clocks (IN 1 , IN 2 ); a pair of tri-state inverters (301, 302) for producing a pair of level signals (V C1 , V C2 ); and a pair of outputs (347, 348) coupled to the level signals (V C1 , V C2 ) for producing a pair of output clocks (OUT 1 , OUT 2 ), wherein the tri-state inverters (301, 302) are responsive to a pair of state signals (S 1 , S 2 ) and the pair of input clocks (IN 1 , IN 2 ) for holding or discharging the level signals (V C1 , V C2 ).

Abstract translation: 时间寄存器（300）包括：耦合到一对输入时钟（IN1，IN2）的一对输入（345,346）; 一对用于产生一对电平信号（VC1，VC2）的三态反相器（301,302）; 以及耦合到电平信号（VC1，VC2）的一对输出（347,348），用于产生一对输出时钟（OUT1，OUT2），其中三态反相器（301,302）响应于一对 状态信号（S1，S2）和用于保持或放电电平信号（VC1，VC2）的一对输入时钟（IN1，IN2）。

公开(公告)号：WO2016119825A1

公开(公告)日：2016-08-04

申请号：PCT/EP2015/051576

申请日：2015-01-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  HUIZHEN, Qian ,  XUN, Luo ,  STASZEWSKI, Robert

Inventor： HUIZHEN, Qian ,  XUN, Luo ,  STASZEWSKI, Robert

IPC: H01F27/28 ,  H01F19/08 ,  H03F1/08 ,  H03F1/22

CPC classification number: H03F1/223 ,  H01F19/08 ,  H01F27/2804 ,  H01F2019/085 ,  H01F2027/2809 ,  H01F2027/2819 ,  H03F1/086 ,  H03F1/56 ,  H03F3/193 ,  H03F3/211 ,  H03F3/2173 ,  H03F3/245 ,  H03F2200/09 ,  H03F2200/451 ,  H03F2200/537 ,  H03F2200/541 ,  H03H7/38 ,  H03H7/42

Abstract: A transformer (400) includes: a primary winding (401) comprising a first port (401a), a second port (401b) and a metal layer (413) connected between the first port (401a) and the second port (401b), the metal layer (413) comprising a plurality of sections (Z 1 /θ 1 , Z 2 /θ 2 , Z 3 /θ 3 , Z 4 /θ 4 ) of different electrical lengths and/or characteristic impedances; and a secondary winding (402) electromagnetically coupled with the primary winding (401), the secondary winding (402) comprising a first port (402a), a second port (402b) and a metal layer (423) connected between the first port (402a) and the second port (402b), the metal layer (423) comprising a plurality of sections (Z 5 /θ 5 , Z 6 /θ 6 , Z 7 /θ 7 , Z 8 /θ 8 , Z 9 /θ 9 , Z 10 /θ 10 ) of different electrical lengths and/or characteristic impedances.

Abstract translation: 变压器（400）包括：初级绕组（401），包括连接在第一端口（401a）和第二端口（401b）之间的第一端口（401a），第二端口（401b）和金属层（413） 所述金属层（413）包括不同电长度和/或特性阻抗的多个部分（Z1 /θ1，Z2 /θ2，Z3 /θ3，Z4 /θ4） 以及与所述初级绕组（401）电磁耦合的次级绕组（402），所述次级绕组（402）包括第一端口（402a），第二端口（402b）和金属层（423），所述第二端口连接在所述第一端口 402a）和第二端口（402b），金属层（423）包括不同电长度的多个部分（Z5 /θ5，Z6 /θ6，Z7 /θ7，Z8 /θ8，Z9 /θ9，Z10 /θ10） 和/或特征阻抗。

公开(公告)号：WO2016119824A1

公开(公告)日：2016-08-04

申请号：PCT/EP2015/051574

申请日：2015-01-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  SHAHMOHAMMADI, Mina ,  BABAIE, Masoud ,  STASZEWSKI, Robert

Inventor： SHAHMOHAMMADI, Mina ,  BABAIE, Masoud ,  STASZEWSKI, Robert

IPC: H03B5/12

CPC classification number: H03B5/1243 ,  H03B5/1218 ,  H03B5/1228 ,  H03B5/1262 ,  H03B5/1296 ,  H03B2201/0266

Abstract: The invention relates to a radio frequency oscillator (100), the radio frequency oscillator (100) comprising a resonator circuit (101) being resonant at an excitation of the resonator circuit (101) in a differential mode and at an excitation of the resonator circuit (101) in a common mode, wherein the resonator circuit (101) has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit (101) has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit (103) being configured to excite the resonator circuit (101) in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit (105) being configured to excite the resonator circuit (101) in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

Abstract translation: 本发明涉及射频振荡器（100），射频振荡器（100）包括谐振电路（101），其在谐振电路（101）的激励下以差分模式谐振，并且谐振电路 （101），其中所述谐振器电路（101）在所述差分模式下的激励时具有差模谐振频率，并且其中所述谐振器电路（101）在所述共模中的激励时具有共模谐振频率 ，第一激励电路（103）被配置为以差分模式激励谐振电路（101），以获得以差模谐振频率振荡的差模振荡器信号，以及第二激励电路（105），其被配置为激励 谐振电路（101），以获得以共模谐振频率振荡的共模振荡器信号。