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11.发明授权公开(公告)号：US12299444B2
公开(公告)日：2025-05-13
申请号：US18323049
申请日：2023-05-24
Applicant: STMicroelectronics International N.V.
Inventor： Sofiane Landi
Abstract: A system includes a memory and a processor coupled to the memory. The processor executes an instruction set having a word size. The processor includes arithmetic processing circuitry, which, in operation, executes arithmetic operations on operands having the word size. The arithmetic processing circuitry includes an arithmetic logic circuit (ALU) having an operand size smaller than the word size of the instruction set. The ALU, in operation, generates partial results of the arithmetic operations. A multiplexing network coupled to inputs of the ALU provides portions of the operands to the ALU. A shift register having the word size of the instruction set accumulates partial results generated by the ALU over a plurality of clock cycles and outputs results of the arithmetic operations based on the accumulated partial results.
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公开(公告)号：US20250151269A1
公开(公告)日：2025-05-08
申请号：US18933452
申请日：2024-10-31
Applicant: STMicroelectronics International N.V.
Inventor： Madjid AKBAL , Franck MELUL , Arnaud REGNIER , Francesco LA ROSA
IPC: H10B41/30 , H01L29/423 , H10B41/10
Abstract: An integrated circuit includes a semiconductor substrate and at least one memory cell provided with a vertical gate selection transistor buried in the substrate and a floating gate state transistor. The floating gate state transistor covers a first active region and a second active region of the substrate delimited by lateral isolation regions. The memory cell includes a lateral isolation region thickness (in breadth) dimension between a sidewall of the vertical gate of the buried transistor and the second active region.
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公开(公告)号：US20250147764A1
公开(公告)日：2025-05-08
申请号：US18913223
申请日：2024-10-11
Applicant: STMicroelectronics International N.V.
Inventor： Philippe Pijourlet , Brice Dufour
Abstract: The present description concerns a device comprising a bus, peripherals coupled to the bus, the peripherals comprising a first circuit, processors coupled to the bus and initiating accesses to the peripherals, each comprising an address phase followed by a data phase, and for each processor, a second circuit delivering an identifier of the processor over the bus during the address phase of each access initiated by the processor. For each read access to the first circuit initiated by one of the processors, the first circuit stores the identifier present over the bus during the address phase of the access, and then delivers the identifier stored over the bus during the data phase of the access.
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公开(公告)号：US20250146159A1
公开(公告)日：2025-05-08
申请号：US18933194
申请日：2024-10-31
Applicant: STMicroelectronics International N.V.
Inventor： Paolo CREMA
Abstract: Articles carried by a carrier are processed in a sequence of processing steps that includes a plating step where a base layer of plating material is plated on a surface of the carrier. The plating material plated on the surface of the carrier is selectively stripped to partially remove the plating material to reduce e thickness of the base layer of plating material plated present on the surface of the carrier. A residual protective layer of plating material having the reduced thickness is left on the surface of the carrier.
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15.发明申请公开(公告)号：US20250145451A1
公开(公告)日：2025-05-08
申请号：US18929345
申请日：2024-10-28
Applicant: STMicroelectronics International N.V.
Inventor： Gabriele GATTERE , Manuel RIANI
Abstract: A microelectromechanical device includes: a supporting body, containing semiconductor material; a movable mass, constrained to the supporting body with a relative degree of freedom with respect to a first motion direction perpendicular to the supporting body; and at least one stopping structure, configured to limit out-of-plane movements of the movable mass along the first motion direction. The stopping structure includes: first elements, extending parallel to the first motion direction and anchoring the stopping structure to the supporting body; and a second element, extending transversally to the first elements, surmounting and connecting the first elements.
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Patent Agency Ranking
公开(公告)号：US20250143193A1
公开(公告)日：2025-05-01
申请号：US18923201
申请日：2024-10-22
Applicant: STMicroelectronics International N.V. , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Inventor： Latifa DESVOIVRES , Jerome DUBOIS , Daniel BENOIT , Pascal GOURAUD
Abstract: The present description relates to a method of manufacturing an electronic device comprising a phase-change memory cell, the method comprising: the forming of a first layer made of a resistive material; the forming of a stack of layers on the first layer, the stack comprising at least one second layer made of a phase-change material; the etching of the stack, said etching stopping when the first layer is reached around the location of the memory cell; the forming of a spacer on the side walls of the stack; then an etching of the first layer, so that the stack rests on a central portion of the first layer and that the spacer rests on a peripheral portion of the first layer.
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公开(公告)号：US20250139265A1
公开(公告)日：2025-05-01
申请号：US18920513
申请日：2024-10-18
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Laurent TABARIES
Abstract: The present disclosure provides a method of storing a data item in an electronic system comprising at least two secure elements, comprising the following successive steps: dividing the data item into at least two parts; and distributing and storing each of the at least two parts into one of the at least two secure elements.
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公开(公告)号：US20250138154A1
公开(公告)日：2025-05-01
申请号：US18915086
申请日：2024-10-14
Applicant: STMicroelectronics International N.V.
Inventor： Yandong MAO , Kai Quan CHENG , Tat Ming TEO , Fraser WILLIAMS , Dominique NUYTS
Abstract: The present disclosure provides an optical sensor module. An example optical sensor module comprises: a light-emitting device; a light-receiving sensor; and a module cap adapted to at least partially cover the light-emitting device and the light-receiving sensor, the module cap comprising a metal casing and a molded part made of a molding material lining the inside surfaces of the metal casing.
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公开(公告)号：US20250132596A1
公开(公告)日：2025-04-24
申请号：US18382776
申请日：2023-10-23
Applicant: STMicroelectronics International N.V.
Inventor： Domenico RAGONESE , Marco MINIERI , Maurizio GRECO , Vincenzo MARANO , Vojtech ELIAS , Milos HOFMAN
Abstract: A power-management system includes a power transistor coupled between a power supply and load, a driver circuit driving the power transistor in response to an input signal, and an error amplifier generating a control signal that modifies operation of the driver circuit based on a comparison between a selected reference voltage and a drain-to-source voltage of the power transistor. A multiplexer provides the selected reference voltage to the error amplifier and passes one of a plurality of different reference voltages as the selected reference voltage based upon first and second selection signals. A first selection circuit charges a first capacitor in response to the input signal and generates the first selection signal based on a first voltage across the first capacitor. A second selection circuit charges a second capacitor in response to the input signal and generates the second selection signal based on a second voltage across the second capacitor.
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20.发明申请公开(公告)号：US20250119065A1
公开(公告)日：2025-04-10
申请号：US18481333
申请日：2023-10-05
Applicant: STMicroelectronics International N.V.
Inventor： Francois TAILLIET , Guglielmo SIRNA
Abstract: A bridge rectifier circuit and a wireless power receiver configured to receive high voltage AC inputs and generate a stable DC voltage without exposing the bridge rectifier circuitry components to damaging high voltages are provided. The example bridge rectifier includes a plurality of rectifying transistors positioned to generate a DC voltage upon receiving an AC current. The example bridge rectifier circuitry further includes voltage control circuitry designed to output an intermediate voltage to a terminal of one or all of the rectifying transistors of the bridge rectifier. The output intermediate voltage prevents a voltage difference across the terminal of the rectifying transistor from exceeding a maximum voltage rating of the rectifying transistor.
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