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    CONTACT DOPING AND ANNEALING SYSTEMS AND PROCESSES FOR NANOWIRE THIN FILMS
    12.
    发明申请
    CONTACT DOPING AND ANNEALING SYSTEMS AND PROCESSES FOR NANOWIRE THIN FILMS 审中-公开
    联系DOPING和退火系统和纳米薄膜的工艺

    公开(公告)号：WO2006057818A3

    公开(公告)日：2008-01-03

    申请号：PCT/US2005040710

    申请日：2005-11-10

    Applicant: NANOSYS INC ,  PAN YAOLING ,  STUMBO DAVID P

    Inventor： PAN YAOLING ,  STUMBO DAVID P

    IPC: B82B1/00 ,  B82B3/00 ,  H01L21/00

    CPC classification number: H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/7606 ,  H01L29/78696 ,  Y10S977/901 ,  Y10S977/963

    Abstract: Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm 2 (e.g., less than about 50 mJ/cm 2 , e.g., between about 2 and 18 mJ/cm 2 ) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.

    Abstract translation: 提供本发明的实施例用于改进的接触掺杂和退火系统和工艺。 在实施例中，等离子体离子浸没注入（PIII）工艺用于纳米线和其它基于纳米元件的薄膜器件的接触掺杂。 根据本发明的另外的实施例，使用在低于约100mJ / cm 2（例如小于约50mJ / cm 2）的较低激光能量密度的激光能量进行脉冲激光退火， SUP>，例如约2和18mJ / cm 2之间）用于退火衬底上的纳米线和其它基于纳米元件的器件，例如低温柔性衬底，例如塑料衬底。

    FULLY INTEGRATED ORGANIC LAYERED PROCESSES FOR MAKING PLASTIC ELECTRONICS BASED ON CONDUCTIVE POLYMERS AND SEMICONDUCTOR NANOWIRES
    14.
    发明申请
    FULLY INTEGRATED ORGANIC LAYERED PROCESSES FOR MAKING PLASTIC ELECTRONICS BASED ON CONDUCTIVE POLYMERS AND SEMICONDUCTOR NANOWIRES 审中-公开

    公开(公告)号：WO2006124055A3

    公开(公告)日：2006-11-23

    申请号：PCT/US2005/034394

    申请日：2005-09-22

    Applicant: NANOSYS, INC. ,  PAN, Yaoling ,  LEON, Francisco, A. ,  STUMBO, David, P.

    Inventor： PAN, Yaoling ,  LEON, Francisco, A. ,  STUMBO, David, P.

    IPC: H01L51/00

    Abstract: The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; deposing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; deposing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; deposing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones on the source and drain regions.

    NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS
    16.
    发明申请
    NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS 审中-公开
    纳米启发的存储器件和执行阵列的各向异性电荷

    公开(公告)号：WO2005089165A2

    公开(公告)日：2005-09-29

    申请号：PCT/US2005007709

    申请日：2005-03-09

    Applicant: NANOSYS INC ,  DUAN XIANGFENG ,  CHOW CALVIN Y H ,  HEALD DAVID L ,  NIU CHUNMING ,  PARCE J WALLACE ,  STUMBO DAVID P

    Inventor： DUAN XIANGFENG ,  CHOW CALVIN Y H ,  HEALD DAVID L ,  NIU CHUNMING ,  PARCE J WALLACE ,  STUMBO DAVID P

    IPC: H01L21/28 ,  H01L29/423 ,  H01L29/788

    CPC classification number: H01L21/28273 ,  B82Y10/00 ,  G03G5/00 ,  G03G5/02 ,  G03G5/04 ,  G03G5/043 ,  G03G5/08 ,  G03G5/082 ,  G03G5/08214 ,  G11C11/56 ,  G11C13/02 ,  G11C13/025 ,  G11C2213/17 ,  G11C2213/18 ,  G11C2216/08 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/7887 ,  Y10S977/774 ,  Y10S977/785 ,  Y10S977/936

    Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    Abstract translation: 描述了用于纳米存储器件和各向异性带电载体阵列的方法和装置。 在一方面，存储器件包括衬底，衬底的源极区域和衬底的漏极区域。 纳米元素的群体沉积在通道区域上方的衬底上，在一个实施方案中纳米元素包括金属量子点。 隧道介电层形成在覆盖沟道区的衬底上，金属迁移势垒层沉积在电介质层上。 在纳米元件的薄膜上形成栅极接触。 纳米元件允许减少横向电荷转移。 存储器件可以是单个或多个存储器件。 在包括具有多个离散能级的一个或多个量子点或分子的多状态存储器件中，公开了用于对该器件进行充电和/或放电的方法，该方法包括填充每个点或分子的多个离散能级中的每一个 与一个或多个电子，并随后从一个或多个点或分子的每个离散能级一次去除单个电子。

    PHASED ARRAY SYSTEMS AND METHODS
    18.
    发明申请
    PHASED ARRAY SYSTEMS AND METHODS 审中-公开
    相控阵列系统和方法

    公开(公告)号：WO2008082654A2

    公开(公告)日：2008-07-10

    申请号：PCT/US2007/026485

    申请日：2007-12-31

    Applicant: NANOSYS, INC. ,  STUMBO, David, P. ,  COMPTON, Richard

    Inventor： STUMBO, David, P. ,  COMPTON, Richard

    IPC: H01Q3/00 ,  H01Q3/12

    CPC classification number: H01Q3/34

    Abstract: A phased array system having antennas, non-variable phase shifters, and switches. The non-variable phase shifters are configured to be coupled selectively to a transmitter or a receiver. A non-variable phase shifter is configured to shift a phase of an electromagnetic energy wave that traverses the non-variable phase shifter by a fraction of a period of the electromagnetic energy wave for a range of frequencies of the electromagnetic energy wave. At least one of the fraction and the range associated with the non-variable phase shifter is different from at least one of the fraction and the range associated with other non-variable phase shifters. The switches are configured to couple selectively the antennas to the non-variable phase shifters, the transmitter, or the receiver.

    Abstract translation: 具有天线，非可变移相器和开关的相控阵系统。 非可变移相器被配置为选择性地耦合到发射机或接收机。 非可变移相器被配置为对于电磁能量波的一定范围的频率，将穿过不可变移相器的电磁能量波的相位偏移电磁能量波的一部分周期。 与非可变移相器相关联的分数和范围中的至少一个不同于与其他非可变移相器相关联的分数和范围中的至少一个。 开关被配置为选择性地将天线耦合到非可变移相器，发射机或接收机。

    METHODS FOR NANOSTRUCTURE DOPING
    20.
    发明申请
    METHODS FOR NANOSTRUCTURE DOPING 审中-公开

    公开(公告)号：WO2007038164A3

    公开(公告)日：2007-04-05

    申请号：PCT/US2006/036738

    申请日：2006-09-21

    Applicant: NANOSYS, INC. ,  PAN, Yaoling ,  CHEN, Jian ,  LEON, Francisco ,  MOSTARSHED, Shahriar ,  ROMANO, Linda T. ,  SAHI, Vijendra ,  STUMBO, David P.

    Inventor： PAN, Yaoling ,  CHEN, Jian ,  LEON, Francisco ,  MOSTARSHED, Shahriar ,  ROMANO, Linda T. ,  SAHI, Vijendra ,  STUMBO, David P.

    IPC: H01L29/06 ,  H01L21/225

    Abstract: Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

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