中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.023 seconds)

    DIELECTRICS USING SUBSTANTIALLY LONGITUDINALLY ORIENTED INSULATED CONDUCTIVE WIRES
    4.
    发明申请
    DIELECTRICS USING SUBSTANTIALLY LONGITUDINALLY ORIENTED INSULATED CONDUCTIVE WIRES 审中-公开

    公开(公告)号：WO2009023061A3

    公开(公告)日：2009-02-19

    申请号：PCT/US2008/007211

    申请日：2008-06-10

    Applicant: NANOSYS, INC. ,  DUBROW, Robert, S. ,  MILLER, Jeffrey ,  STUMBO, David, P.

    Inventor： DUBROW, Robert, S. ,  MILLER, Jeffrey ,  STUMBO, David, P.

    IPC: H01L21/469

    Abstract: A dielectric material is disclosed comprising a plurality of substantially longitudinally oriented wires which are coupled together, wherein each of the wires includes a conductive core comprising a first material and one or more insulating shell layers comprising a compositionally different second material disposed about the core. In one embodiment, a dielectric layer is disclosed comprising a substrate comprising an insulating material having a plurality of nanoscale pores defined therein having a pore diameter less than about 100 nm, and a conductive material disposed within the nanoscale pores. Methods are also disclosed to create a dielectric material layer comprising, for example, providing a plurality of wires, wherein each of the wires includes a core comprising a first material and one or more insulating layers comprising a compositionally different second material disposed about the core; substantially longitudinally orienting said plurality of wires along their long axes; coupling the wires together; and depositing an insulating coating on at least one of a top and/or a bottom end of the wires.

    METHODS FOR NANOSTRUCTURE DOPING
    6.
    发明申请
    METHODS FOR NANOSTRUCTURE DOPING 审中-公开
    用于纳米结构的方法

    公开(公告)号：WO2007038164A2

    公开(公告)日：2007-04-05

    申请号：PCT/US2006036738

    申请日：2006-09-21

    Applicant: NANOSYS INC ,  PAN YAOLING ,  CHEN JIAN ,  LEON FRANCISCO ,  MOSTARSHED SHAHRIAR ,  ROMANO LINDA T ,  SAHI VIJENDRA ,  STUMBO DAVID P

    Inventor： PAN YAOLING ,  CHEN JIAN ,  LEON FRANCISCO ,  MOSTARSHED SHAHRIAR ,  ROMANO LINDA T ,  SAHI VIJENDRA ,  STUMBO DAVID P

    IPC: H01L29/06 ,  H01L21/225

    CPC classification number: H01L29/0665 ,  B81C1/00698 ,  B81C2201/0173 ,  B82Y10/00 ,  H01L21/2256 ,  H01L21/268 ,  H01L29/0673

    Abstract: Methods of doping nanostructures, such as nanowires, are disclosed. The methods provide a variety of approaches for improving existing methods of doping nanostructures. The embodiments include the use of a sacrificial layer to promote uniform dopant distribution within a nanostructure during post-nanostructure synthesis doping. In another embodiment, a high temperature environment is used to anneal nanostructure damage when high energy ion implantation is used. In another embodiment rapid thermal annealing is used to drive dopants from a dopant layer on a nanostructure into the nanostructure. In another embodiment a method for doping nanowires on a plastic substrate is provided that includes depositing a dielectric stack on a plastic substrate to protect the plastic substrate from damage during the doping process. An embodiment is also provided that includes selectively using high concentrations of dopant materials at various times in synthesizing nanostructures to realize novel crystallographic structures within the resulting nanostructure.

    Abstract translation: 公开了掺杂纳米结构的方法，例如纳米线。 该方法提供了改进现有的纳米结构掺杂方法的各种方法。 实施例包括在后纳米结构合成掺杂期间使用牺牲层来促进纳米结构内的均匀掺杂剂分布。 在另一个实施例中，当使用高能离子注入时，使用高温环境退火纳米结构损伤。 在另一个实施方案中，使用快速热退火来将掺杂剂从纳米结构上的掺杂剂层驱动到纳米结构中。 在另一个实施例中，提供了一种在塑料衬底上掺杂纳米线的方法，其包括在塑料衬底上沉积电介质叠层以保护塑料衬底免于在掺杂过程期间损坏。 还提供了一种实施方案，其包括在合成纳米结构中在不同时间选择性地使用高浓度的掺杂剂材料，以在所得纳米结构内实现新的晶体结构。

    NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS
    8.
    发明申请
    NANO-ENABLED MEMORY DEVICES AND ANISOTROPIC CHARGE CARRYING ARRAYS 审中-公开

    公开(公告)号：WO2005089165A3

    公开(公告)日：2005-09-29

    申请号：PCT/US2005/007709

    申请日：2005-03-09

    Applicant: NANOSYS, INC. ,  DUAN, Xiangfeng ,  CHOW, Calvin, Y., H. ,  HEALD, David, L. ,  NIU, Chunming ,  PARCE, J., Wallace ,  STUMBO, David, P.

    Inventor： DUAN, Xiangfeng ,  CHOW, Calvin, Y., H. ,  HEALD, David, L. ,  NIU, Chunming ,  PARCE, J., Wallace ,  STUMBO, David, P.

    IPC: H01L29/06

    Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.

    DIELECTRICS USING SUBSTANTIALLY LONGITUDINALLY ORIENTED INSULATED CONDUCTIVE WIRES
    10.
    发明申请
    DIELECTRICS USING SUBSTANTIALLY LONGITUDINALLY ORIENTED INSULATED CONDUCTIVE WIRES 审中-公开
    介质使用大体垂直绝缘导电线

    公开(公告)号：WO2009023061A2

    公开(公告)日：2009-02-19

    申请号：PCT/US2008007211

    申请日：2008-06-10

    Applicant: NANOSYS INC ,  DUBROW ROBERT S ,  MILLER JEFFREY ,  STUMBO DAVID P

    Inventor： DUBROW ROBERT S ,  MILLER JEFFREY ,  STUMBO DAVID P

    IPC: H01G4/10

    CPC classification number: H01B7/0009 ,  B82Y99/00 ,  H01B3/004 ,  H01G4/018 ,  H01G4/20 ,  Y10T428/249924

    Abstract: A dielectric material is disclosed comprising a plurality of substantially longitudinally oriented wires which are coupled together, wherein each of the wires includes a conductive core comprising a first material and one or more insulating shell layers comprising a compositionally different second material disposed about the core. In one embodiment, a dielectric layer is disclosed comprising a substrate comprising an insulating material having a plurality of nanoscale pores defined therein having a pore diameter less than about 100 nm, and a conductive material disposed within the nanoscale pores. Methods are also disclosed to create a dielectric material layer comprising, for example, providing a plurality of wires, wherein each of the wires includes a core comprising a first material and one or more insulating layers comprising a compositionally different second material disposed about the core; substantially longitudinally orienting said plurality of wires along their long axes; coupling the wires together; and depositing an insulating coating on at least one of a top and/or a bottom end of the wires.

    Abstract translation: 公开了一种介电材料，其包括多个基本上纵向定向的导线，所述导线耦合在一起，其中每个导线包括包含第一材料的导电芯和包含围绕芯设置的组成不同的第二材料的一个或多个绝缘壳层。 在一个实施例中，公开了一种介电层，该介电层包括含有绝缘材料的衬底和设置在纳米级孔内的导电材料，绝缘材料具有限定在其中的多个纳米级孔隙，孔隙直径小于约100nm。 还公开了制造电介质材料层的方法，该电介质材料层例如包括提供多个导线，其中每个导线包括包含第一材料的芯和包含围绕芯布置的组成不同的第二材料的一个或多个绝缘层; 使所述多根丝线沿其长轴基本纵向定向; 将导线连接在一起; 以及在导线的顶端和/或底端中的至少一个上沉积绝缘涂层。

Patent Agency Ranking