公开(公告)号：KR1020000001683A

公开(公告)日：2000-01-15

申请号：KR1019980022053

申请日：1998-06-12

Applicant: 삼성전자주식회사

Inventor： 김국민 ,  윤광준

IPC: H01L21/336

Abstract: PURPOSE: A semiconductor device forming method is provided to reduce a cost by varying a process so as to form a transistor of a lightly doped drain(LDD) structure without forming a separate spacer. CONSTITUTION: The method of forming a semiconductor device comprises the steps of: sequentially forming a gate insulating layer(102) and a conductive layer(104) on a semiconductor substrate(100); forming a photosensitive layer pattern(106) at a part of the conductive layer, wherein a width of the photosensitive layer pattern is "S+2d"(S: a width of a gate electrode determined by a design rule, d: a width of a conventional spacer); etching the conductive layer by use of the photosensitive layer pattern as a mask to form a conductive pattern(104a) of a predetermined size; implanting a heavily doped impurity of a first conductive type to the substrate to form source and drain regions(108) in the substrate and at both edges of the conductive pattern; etching both sides of the photosensitive pattern and a top side thereof to form the width of the photosensitive pattern with a "S" shape; etching the conductive pattern by use of the photosensitive pattern of the "S" shape as a mask to form a gate electrode(104b); implanting a lightly doped impurity of the first conductive type to the substrate to form a lightly doped drain region, adjacent to the source and drain regions, in the substrate and at both edges of the gate electrode; and etching the gate insulating layer by use of the photosensitive pattern of the "S" shape as a mask to remove the photosensitive layer pattern.

Abstract translation: 目的：提供一种半导体器件形成方法，通过改变处理以便形成轻掺杂漏极（LDD）结构的晶体管而不形成单独的间隔物来降低成本。 构成：形成半导体器件的方法包括以下步骤：在半导体衬底（100）上依次形成栅极绝缘层（102）和导电层（104）; 在导电层的一部分形成感光层图案（106），其中感光层图案的宽度为“S + 2d”（S：由设计规则确定的栅电极的宽度，d： 常规垫片）; 通过使用感光层图案作为掩模来蚀刻导电层以形成预定尺寸的导电图案（104a）; 将第一导电类型的重掺杂杂质注入衬底以在衬底中并在导电图案的两个边缘处形成源区和漏区（108）; 蚀刻感光图案的两侧和其顶侧以形成具有“S”形状的感光图案的宽度; 通过使用“S”形状的感光图案作为掩模来蚀刻导电图案以形成栅电极（104b）; 将第一导电类型的轻掺杂杂质注入衬底以在衬底中并且在栅电极的两个边缘处形成与源极和漏极区相邻的轻掺杂漏极区; 并且通过使用“S”形状的感光图案作为掩模来蚀刻栅极绝缘层以去除感光层图案。