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公开(公告)号：KR1020070058422A
公开(公告)日：2007-06-08
申请号：KR1020070049761
申请日：2007-05-22
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1096 , G11C7/06 , G11C7/18 , G11C2207/2227
Abstract: A semiconductor memory device having an advanced data input/output path is provided to reduce power consumption by reducing the path where data is fully swung to a CMOS level during a data read operation. A semiconductor memory device has a write driving circuit to write data in a memory cell. The write driving circuit includes a first write driver part and a second write driver part. The first write driver part drives data with a smaller level than data to be written in the memory cell and then outputs the data to a first data input line pair. The second write driver part receives data from the first write driver part and then drives the data to the data level to be written in the memory cell, and then provides the data to a selection bit line pair connected to the memory cell.
Abstract translation: 提供具有高级数据输入/输出路径的半导体存储器件，以在数据读取操作期间将数据完全摆动到CMOS电平的路径减少功率消耗。 半导体存储器件具有写入驱动电路以将数据写入存储单元。 写入驱动电路包括第一写入驱动器部分和第二写入驱动器部分。 第一写入驱动器部分驱动比要写入存储器单元的数据更小的数据，然后将数据输出到第一数据输入线对。 第二写入驱动器部分从第一写入驱动器部分接收数据，然后将数据驱动到要写入存储器单元的数据级，然后将数据提供给连接到存储器单元的选择位线对。
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公开(公告)号：KR1020070058421A
公开(公告)日：2007-06-08
申请号：KR1020070049759
申请日：2007-05-22
Applicant: 삼성전자주식회사
CPC classification number: G11C7/18 , G11C7/06 , G11C7/12 , G11C2207/002
Abstract: A semiconductor memory device having an advanced data input/output path of a hierarchical bit line structure is provided to prevent the decrease of operation speed due to a load of peripheral circuits connected to a bit line. In a semiconductor memory device having an advanced data input/output path, a plurality of memory blocks includes a plurality of bit line pairs. First sense amplifiers are arranged per I/O port in the memory blocks, and sense and amplify data shown in a pair of bit lines selected by an address, to a first level. Second sense amplifiers are arranged in read section data line pairs, respectively, in order to sense and amplify data shown in read section data line pairs of the first sense amplifiers connected to memory blocks arranged in a first direction, to a second level higher than the first level.
Abstract translation: 提供了具有分级位线结构的高级数据输入/输出路径的半导体存储器件，以防止由于与位线连接的外围电路的负载引起的操作速度的降低。 在具有高级数据输入/输出路径的半导体存储器件中，多个存储块包括多个位线对。 第一读出放大器按照存储器块中的每个I / O端口布置，并且将由地址选择的一对位线中显示的数据检测和放大到第一级。 第二读出放大器分别被布置在读部分数据线对中，以便感测和放大连接到以第一方向布置的存储块的第一读出放大器的读部分数据线对中所示的数据，高于 一级
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公开(公告)号：KR1020050072205A
公开(公告)日：2005-07-11
申请号：KR1020040000517
申请日：2004-01-06
Applicant: 삼성전자주식회사
IPC: H03H3/00
CPC classification number: H04L25/0278 , H03K19/00384 , H04L25/028
Abstract: 본 발명은 임피던스 컨트롤 장치 및 그에 따른 컨트롤 방법에 관한 것으로, 본 발명에 따른 임피던스 컨트롤 장치는, 임피던스 전류를 발생시키는 전류미러부와, 트랜지스터 어레이로 구성되어 상기 임피던스 전류에 상응하는 임피던스를 갖도록 코드 발생기에 의해 컨트롤되는 적어도 하나 이상의 디텍터와, 상기 디텍터의 출력과 기준 전압을 비교하여 상기 디텍터를 구성하는 트랜지스터 어레이의 게이트 전압을 조절하기 위한 제1코드를 발생시켜 상기 디텍터의 출력을 조절하고, 상기 임피던스 전류에 근접하거나 일치되는 때에 발생된 제1코드에 응답하는 상기 디텍터의 출력과 기준전압을 비교하여, 상기 디텍터를 구성하는 트랜지스터 어레이의 사이즈를 조절하기 위한 제2코드를 발생시켜 상기 디텍터를 컨트롤하는 적어도 하나 이상의 코드 발 생기를 구비함을 특징으로 한다. 본 발명에 따르면, 외부 저항이 다른 경우에도 일정한 임피던스 해상도를 가질 수 있으며, 공정 변화나 환경변화에 관계없이 일정한 임피던스 해상도를 얻을 수 있다.
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公开(公告)号：KR1020050039230A
公开(公告)日：2005-04-29
申请号：KR1020030074660
申请日：2003-10-24
Applicant: 삼성전자주식회사
IPC: H01L23/28
CPC classification number: H01L24/11 , H01L24/02 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/1147 , H01L2224/13078 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/1411 , H01L2924/0001 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/351 , H01L2924/0105 , H01L2924/00014 , H01L2924/00
Abstract: 초박형의 플립칩 패키지의 제조방법을 제공한다. 본 발명은 반도체 칩의 금속 패드 상에 하부 배리어 금속막을 형성하고, 상기 하부 배리어 금속막 상에, 기둥부와 상기 기둥부의 상부 부분은 버섯부로 구성된 3차원 구조의 솔더 범프를 형성한다. 상기 3차원 구조의 솔더 범프를 포함하는 반도체 칩을 뒤집어서 인쇄회로기판 상의 솔더층과 접합하여 플립칩 패키지를 완성한다. 본 발명은 3차원 구조의 솔더 범프를 채용하여 솔더 범프의 높이를 낮출 수 있어 초박형과 구조적인 신뢰성이 향상된 플립칩 패키지를 구현할 수 있다.
Abstract translation: 提供一种制造超薄倒装芯片封装的方法。 在上述方法中，在半导体芯片的接合焊盘上形成下阻挡金属膜。 在下阻挡金属膜上形成三维结构化的焊料凸块。 每个焊料凸块包括设置在棒部的端部的棒部和球部。 包括三维结构的焊料凸块的半导体芯片被结合到印刷电路板上的焊料层以完成倒装芯片封装。 根据本发明，通过采用三维结构化的焊料凸点，可以降低焊锡凸块的高度，从而提高超薄倒装芯片封装的可靠性。
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公开(公告)号：KR100426990B1
公开(公告)日：2004-04-13
申请号：KR1020010036883
申请日：2001-06-27
Applicant: 삼성전자주식회사
IPC: G01R1/10
CPC classification number: G05F1/577
Abstract: A reference voltage generating circuit includes a binary-to-thermometer for converting binary codes into thermometer codes; an internal reference voltage generator for generating an internal reference voltage in response to the thermometer codes from the binary-to-thermometer, wherein the internal reference voltage generator changes a level of the internal reference voltage in response to the thermometer codes; a selector for selecting the internal reference voltage or an external reference voltage in response to a reference voltage select signal; and a voltage regulator for regulating a reference voltage selected by the selector.
Abstract translation: 参考电压产生电路包括用于将二进制码转换成温度计码的二进制到温度计; 内部参考电压发生器，用于响应来自二进制到温度计的温度计码而产生内部参考电压，其中内部参考电压发生器响应于温度计码而改变内部参考电压的电平; 选择器，用于响应于参考电压选择信号来选择内部参考电压或外部参考电压; 以及用于调节由选择器选择的参考电压的电压调节器。
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Patent Agency Ranking
公开(公告)号：KR100422447B1
公开(公告)日：2004-03-11
申请号：KR1020010062065
申请日：2001-10-09
Applicant: 삼성전자주식회사
IPC: H03K19/0175
CPC classification number: H03K3/356113 , H03K3/356165 , H03K5/06
Abstract: A converter (110) outputs a level-converted signal in response to an input signal. A delay unit (120) delays the level converted signal, by a predetermined time. A self-reset unit (130) generates a reset signal in response to the delayed level converted signal so that the pulse width of level converted signal is set as the sum of predetermined delay time and an internal operation delay time. Independent claims are also included for the following: (1) signal converting apparatus; (2) level converting method and (3) signal converting method.
Abstract translation: A转换器（110）响应于输入信号输出电平转换的信号。 延迟单元（120）将电平转换后的信号延迟预定时间。 自复位单元（130）响应于延迟电平转换信号产生复位信号，使得电平转换信号的脉冲宽度被设置为预定延迟时间和内部操作延迟时间之和。 独立权利要求还包括以下内容：（1）信号转换设备; （2）电平转换方法和（3）信号转换方法。
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公开(公告)号：KR100422442B1
公开(公告)日：2004-03-11
申请号：KR1020000074595
申请日：2000-12-08
Applicant: 삼성전자주식회사
IPC: G11C8/00
CPC classification number: H03H11/26 , H03K5/133 , H03K2005/00039 , H03K2005/0013 , H03K2005/00143
Abstract: A delay circuit having a constant period of delay time independent of changes in operations, temperature and voltage includes a current source for generating a constant current and having PMOS transistors of which gates are commonly connected, wherein the constant current is controlled by sizes of the PMOS transistors; and a unit delay circuit including a CMOS inverter having PMOS and NMOS transistors, wherein non-adjacent PMOS and NMOS transistors are controlled to charge and discharge current when a constant level of the constant current is transmitted from the current source and other adjacent PMOS and NMOS transistors are switched to connect or disconnect a current path through which the current is charged or discharged.
Abstract translation: 具有与操作，温度和电压的变化无关的恒定延迟时间周期的延迟电路包括用于产生恒定电流的电流源和具有栅极共同连接的PMOS晶体管，其中恒定电流由PMOS的尺寸 晶体管; 以及包括具有PMOS和NMOS晶体管的CMOS反相器的单位延迟电路，其中当恒定电流的恒定电平从电流源和其他相邻的PMOS和NMOS传送时，控制非相邻的PMOS和NMOS晶体管以充电和放电电流 开关晶体管以连接或断开电流通过其充电或放电的电流路径。
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公开(公告)号：KR100394586B1
公开(公告)日：2003-08-14
申请号：KR1020000071832
申请日：2000-11-30
Applicant: 삼성전자주식회사
IPC: H03H3/00
CPC classification number: G05F1/46
Abstract: An impedance control circuit that reduces the impedance variance when an external impedance generated from an external resistor is matched to internal impedance. In one aspect, an impedance control circuit comprises an external resistor for establishing a first reference voltage; a comparator for comparing the first reference voltage with a second reference voltage and outputting an impedance corresponding to the result of the comparison; and a PMOS current source connected to a constant-voltage source and to the output of the comparator, wherein the PMOS current source generates a current that corresponds to the impedance of the comparator.
Abstract translation: 阻抗控制电路，用于在外部电阻产生的外部阻抗与内部阻抗匹配时降低阻抗变化。 在一个方面，阻抗控制电路包括用于建立第一参考电压的外部电阻器; 比较器，用于将第一参考电压与第二参考电压进行比较，并输出与比较结果对应的阻抗; 以及与恒定电压源和比较器的输出端连接的PMOS电流源，其中PMOS电流源产生与比较器的阻抗对应的电流。
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公开(公告)号：KR100394575B1
公开(公告)日：2003-08-14
申请号：KR1020010019153
申请日：2001-04-11
Applicant: 삼성전자주식회사
IPC: G11C29/00
CPC classification number: G11C29/12005 , G01R31/318572 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C2029/3202
Abstract: A circuit and method for selectively outputting internal information in a semiconductor memory device comprising a test circuit such as a JTAG test circuit. The internal information is selectively output through a test pin of the test circuit during a normal operation mode of the semiconductor memory. The internal information of a semiconductor memory chip is output as either a digital or analog signal without having to add additional package pins.
Abstract translation: 用于在包括诸如JTAG测试电路的测试电路的半导体存储器件中选择性地输出内部信息的电路和方法。 在半导体存储器的正常操作模式期间，内部信息通过测试电路的测试引脚被选择性地输出。 半导体存储器芯片的内部信息可以作为数字或模拟信号输出，无需添加额外的封装引脚。
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公开(公告)号：KR100391148B1
公开(公告)日：2003-07-16
申请号：KR1020000064830
申请日：2000-11-02
Applicant: 삼성전자주식회사
IPC: G05B19/00
CPC classification number: H03K19/0005
Abstract: A programmable impedance control circuit for detecting a characteristic impedance of transmission line to thereby output it to an output driver and on-chip terminator in a semiconductor device. Particularly the circuit serves to control an internal impedance according to a controlled, programmable protocol irrespective of the changes in an external impedance due to factors such as voltage and temperature after an initial internal impedance is set during a locking operation.
Abstract translation: 一种可编程阻抗控制电路，用于检测传输线的特性阻抗，从而将其输出到半导体器件中的输出驱动器和片上终端器。 具体地，该电路用于根据受控的可编程协议来控制内部阻抗，而不管在锁定操作期间初始内部阻抗被设置之后由于诸如电压和温度等因素的外部阻抗的变化。
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