公开(公告)号：KR1020060113248A

公开(公告)日：2006-11-02

申请号：KR1020050036528

申请日：2005-04-30

Applicant: 삼성전자주식회사

Inventor： 최상익 ,  박향숙

IPC: G06F13/16 ,  G06F13/28 ,  G06F12/00

CPC classification number: G06F13/28 ,  G06F9/4403

Abstract: A device and a method for controlling a NAND flash memory are provided to increase a data transfer rate, reduce a chip size, and shorten booting time by controlling data transfer between the NAND flash memory and a CPU with a DMA(Direct Memory Access) mode. A register(150) stores an operation command from the CPU(180) and information related to the operation command. A boot SRAM(130) stores a boot code for initializing a system. A DMA controller(140) transfers data of the NAND flash memory(170) to a main memory(190) without passing the CPU. A state machine(110) controls the NAND flash memory. An ECC(Error Checking and Correction Code) circuit(160) detects and corrects a physical error of the NAND flash memory. The DMA controller includes the first internal memory for receiving the data from the NAND flash memory and transferring the received data to the main memory according to a control signal of the state machine.

Abstract translation: 提供一种用于控制NAND闪速存储器的装置和方法，以通过控制NAND闪速存储器与具有DMA（直接存储器访问）模式的CPU之间的数据传输来增加数据传输速率，减小芯片尺寸并缩短启动时间 。 寄存器（150）存储来自CPU（180）的操作命令和与操作命令有关的信息。 引导SRAM（130）存储用于初始化系统的引导代码。 DMA控制器（140）在不通过CPU的情况下将NAND闪存（170）的数据传送到主存储器（190）。 状态机（110）控制NAND闪速存储器。 ECC（错误检查和校正码）电路（160）检测并校正NAND闪存的物理错误。 DMA控制器包括用于从NAND闪速存储器接收数据的第一内部存储器，并且根据状态机的控制信号将接收到的数据传送到主存储器。