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公开(公告)号：KR1019880001011B1
公开(公告)日：1988-06-13
申请号：KR1019850002597
申请日：1985-04-15
Applicant: 삼성전자주식회사
Inventor： 변형구
IPC: G06F7/52
Abstract: When two applied data symbols are designated by X(A0-A7), Y(B0-B7), the data symbol X(A0-A7) is divided into upper bits (A4-7) and lower bits (A0-3) and is applied in series. The data symbol Y(B0-7) is applied in parallel. After the two data symbols are processed to the ratio of 1:8, their output w.r.t. the two data symbols is treated as the data in finite field. The separated data is applied to the parallel/series converter (P/S converter) (10) (20) in parallel and the one bit of the separated data is connected to the AND gates (AN1, AN2).
Abstract translation: 当由X（A0-A7），Y（B0-B7）指定两个应用的数据符号时，数据符号X（A0-A7）被分成高位（A4-7）和低位（A0-3）和 串联应用。 数据符号Y（B0-7）并行应用。 在两个数据符号被处理为1：8的比率之后，它们的输出w.r.t. 将两个数据符号视为有限域中的数据。 分离的数据并行施加到并行/串联转换器（10）（20），分离数据的一位连接到与门（AN1，AN2）。
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Patent Agency Ranking
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公开(公告)号：KR1019930009699B1
公开(公告)日：1993-10-08
申请号：KR1019900014824
申请日：1990-09-19
Applicant: 삼성전자주식회사
IPC: G11B27/02
CPC classification number: H04N5/9205 , H04N9/8227
Abstract: The double reproducing circuit includes first and second video signal inputs, first and second vertical sync. detectors for receiving first and second image signals and detecting vertical sync. signals, a first A/D converter for converting the second image signal into a digital signal, a recording controller for receiving the vertical sync. signals detected by the first and second vertical sync. detectors and generating a first memory control signal, a first mixing control signal, and a first selection control signal, a first memory for receiving the digital signal converted by the A/D converter and performing recording/reproducing under control of the first memory control signal, a first D/A converter for converting the analog second image signal after receiving the signal read out by the first memory, a first mixer for receiving the analog second image signal and the first image signal and selectively outputting them, and a first selector for selectively outputting the output of the first mixer and the input signals into the first and second video signal inputs.
Abstract translation: 双重再现电路包括第一和第二视频信号输入，第一和第二垂直同步。 用于接收第一和第二图像信号和检测垂直同步的检测器。 信号，用于将第二图像信号转换为数字信号的第一A / D转换器，用于接收垂直同步的记录控制器。 由第一和第二垂直同步检测的信号。 检测器并产生第一存储器控制信号，第一混合控制信号和第一选择控制信号;第一存储器，用于接收由A / D转换器转换的数字信号，并在第一存储器控制信号的控制下执行记录/再现 ，用于在接收到由第一存储器读出的信号之后转换模拟第二图像信号的第一D / A转换器，用于接收模拟第二图像信号和第一图像信号并选择性地输出模拟第二图像信号的第一选择器， 选择性地将第一混频器的输出和输入信号输出到第一和第二视频信号输入端。
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