公开(公告)号：KR1020120136116A

公开(公告)日：2012-12-18

申请号：KR1020110055134

申请日：2011-06-08

Applicant: 삼성전자주식회사

Inventor： 송영선 ,  김보근 ,  박기태 ,  권오석 ,  윤상용 ,  신승환

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3459

Abstract: PURPOSE: A nonvolatile memory device and a programming method thereof are provided to improve a program pass/fail checking speed by increasing the number of fail bits which are counted. CONSTITUTION: A page buffer unit(120) is connected to a memory cell array through bit lines. A page buffer decoding unit successively outputs a current according to the number of fail bits at each group. An analog bit counting unit(160) successively counts a current which is successively outputted from the page buffer decoding unit. A digital adding unit(170) calculates a cumulative sum of a count result from the analog bit counting unit. A pass/fail checking unit(180) outputs a pass signal or fail signal according to the sum result. A control unit controls the following program operation in response to the pass signal or fail signal.

Abstract translation: 目的：提供非易失性存储器件及其编程方法，通过增加计数的故障位数来提高程序通过/失败检查速度。 构成：页缓冲单元（120）通过位线连接到存储单元阵列。 页缓冲器解码单元根据每组的故障比特数依次输出电流。 模拟比特计数单元（160）对从页缓冲器解码单元连续输出的电流进行连续计数。 数字添加单元（170）计算来自模拟比特计数单元的计数结果的累积和。 通过/失败检查单元（180）根据求和结果输出通过信号或失败信号。 控制单元响应于通过信号或失败信号来控制以下程序操作。