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公开(公告)号：KR101802815B1
公开(公告)日：2017-12-29
申请号：KR1020110055134
申请日：2011-06-08
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/08 , G11C16/34 , G11C16/3459
Abstract: 본발명은불휘발성메모리장치에관한것이다. 본발명의불휘발성메모리장치는메모리셀 어레이, 검증읽기결과를출력하는페이지버퍼부, 기준전류신호를생성하는기준전류생성부, 검증읽기결과에따라전류를출력하는페이지버퍼디코딩부, 전류를카운트는아날로그비트카운팅부, 카운팅결과의누적합을계산하는디지털합산부, 디지털합산부의계산결과에따라패스신호또는페일신호를출력하도록구성되는패스/페일체킹부, 그리고후속프로그램동작을제어하도록구성되는제어부를포함하는불휘발성메모리장치.
Abstract translation: 本发明涉及一种非易失性存储器件。 本发明的非易失性存储器件具有存储单元阵列，用于输出所述缓冲部的结果，验证读出的页，所述参考电流发生器产生一个基准电流信号，基于该结果页缓冲器中的验证读取用于输出当前译码单元，计数的当前 根据数字求和单元的计算结果输出通过信号或失败信号的失败检查单元以及被配置为控制随后的编程操作的通过/失败检查单元 一种包括控制部分的非易失性存储器件。
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公开(公告)号：KR1020140065185A
公开(公告)日：2014-05-29
申请号：KR1020120132420
申请日：2012-11-21
Applicant: 삼성전자주식회사
CPC classification number: G11C16/08 , G11C7/04 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26
Abstract: The present invention relates to a semiconductor memory device which applies a temperature-compensated word line voltage to a word line in a data reading operation. In the present invention, disclosed is the semiconductor memory device comprising a memory cell array which includes a plurality of word lines, a plurality of bit lines, and a plurality of nonvolatile memory cells which are connected to the word lines and the bit lines; and a word line voltage applying unit which applies a temperature-compensated read voltage to a selected word line and applies a temperature-compensated pass voltage to an unselected word line in the reading operation.
Abstract translation: 半导体存储器技术领域本发明涉及在数据读取操作中将温度补偿字线电压施加到字线的半导体存储器件。 在本发明中，公开了包括存储单元阵列的半导体存储器件，该存储单元阵列包括连接到字线和位线的多个字线，多个位线和多个非易失性存储器单元; 以及字线电压施加单元，其对所选择的字线施加温度补偿读取电压，并且在读取操作中将温度补偿通过电压施加到未选择的字线。
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公开(公告)号：KR1020100104840A
公开(公告)日：2010-09-29
申请号：KR1020090023509
申请日：2009-03-19
Applicant: 삼성전자주식회사
IPC: G11C29/42
CPC classification number: H03M13/13 , G06F11/1072 , H03M13/2906 , H03M13/356
Abstract: PURPOSE: The electronic system including the semiconductor memory device capable of the addition ECC according to the cell pattern, and the apparatus is proceed the ECC encoding based on the specific cell pattern. The data error generation of the vulnerable cell is prevented. CONSTITUTION: A memory cell array(530) stores user data. The ECC engine(790) is proceed the first ECC encoding about user data. The ECC engine outputs the first ECC encoding result of training as ECC information data. The ECC engine detects the cell pattern predetermined based on user data. The ECC engine is proceed the second ECC encoding about cell data corresponding to the cell pattern.
Abstract translation: 目的：包括能够根据单元图案的加法ECC的半导体存储器件的电子系统，并且该装置基于特定单元图案进行ECC编码。 防止易受攻击的小区的数据错误生成。 构成：存储单元阵列（530）存储用户数据。 ECC引擎（790）进行关于用户数据的第一ECC编码。 ECC引擎将训练的第一ECC编码结果作为ECC信息数据输出。 ECC引擎基于用户数据检测预定的单元格图案。 ECC引擎进行关于对应于单元格图案的单元数据的第二ECC编码。
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Patent Agency Ranking
公开(公告)号：KR1020100041470A
公开(公告)日：2010-04-22
申请号：KR1020080100672
申请日：2008-10-14
Applicant: 삼성전자주식회사
CPC classification number: G11C7/18 , G11C5/147 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2207/002
Abstract: PURPOSE: A non-volatile memory device is provided to reduce current consumption in a column driver by using a column selection circuit which selects one bit line among a plurality of bit lines. CONSTITUTION: A memory cell array(10) comprises a matrix of a plurality of nonvolatile memory cells. A plurality of bit lines are coupled with the column of nonvolatile memory cells within a memory cell array. A column selection circuit(50) answers to a column selection signal. The column selection circuit selects at least one bit line among a plurality of bit lines. A column driver(200) outputs the column selection signal.
Abstract translation: 目的：提供一种非易失性存储器件，通过使用在多个位线中选择一个位线的列选择电路来减少列驱动器中的电流消耗。 构成：存储单元阵列（10）包括多个非易失性存储单元的矩阵。 多个位线与存储单元阵列内的非易失性存储单元列耦合。 列选择电路（50）应答列选择信号。 列选择电路选择多个位线中的至少一个位线。 列驱动器（200）输出列选择信号。
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7.发明公开셀의 위치를 고려하여 니어-셀과 파-셀간 동작 전압의 차이를 보상하는 반도체 메모리 장치, 그를 포함하는 메모리 카드 및 메모리 시스템 无效用于补充细胞和细胞之间在细胞位置的细胞和细胞之间的电流差异的补偿的半导体存储器件
公开(公告)号：KR1020100084285A
公开(公告)日：2010-07-26
申请号：KR1020090003688
申请日：2009-01-16
Applicant: 삼성전자주식회사
CPC classification number: G11C5/02 , G11C5/147 , G11C7/12 , G11C7/18 , G11C8/08 , G11C16/24 , G11C29/816 , G11C2207/002
Abstract: PURPOSE: A semiconductor memory device is provided to compensate the current difference between a near-cell and a far-cell based on the cell position in a memory card and a memory system. CONSTITUTION: A memory cell array comprises memory cells which are arranged therein in a matrix. More than two local bit lines(BL0-BL7) are respectively connected to more than two global bit line(GBL0,GBL1). Bit lines comprises local bit lines which are coupled with the row of the memory cells within the memory cell array. A plurality of bit line selection drivers are connected to the local bit lines. An internal boost power generating unit generates internal boost power having different levels more than 2.
Abstract translation: 目的：提供一种半导体存储器件，用于基于存储卡和存储器系统中的单元位置来补偿近电池和远电池之间的电流差。 构成：存储单元阵列包括以矩阵形式布置在其中的存储单元。 多于两个本地位线（BL0-BL7）分别连接到两个以上的全局位线（GBL0，GBL1）。 位线包括与存储器单元阵列内的存储单元的行耦合的局部位线。 多个位线选择驱动器连接到局部位线。 一个内部升压发电单元产生具有不同于2的水平的内部升压功率。
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公开(公告)号：KR1020100090968A
公开(公告)日：2010-08-18
申请号：KR1020090010221
申请日：2009-02-09
Applicant: 삼성전자주식회사
CPC classification number: G11C16/3418 , G11C16/24 , G11C16/3427
Abstract: PURPOSE: A nonvolatile memory device and a programming method thereof are provided to prevent non-selected memory cell from being programmed by differently setting a bias condition for self boosting in a program operation. CONSTITUTION: A memory cell array(110) includes a plurality of memory cells. A control logic unit(120) programs the plurality of memory cells and divides a plurality of program loops into two program loop sections. The control logic unit differently sets a bias condition for self boosting at each program loop section. A voltage generator(130) generates voltages to be applied to a selected word line, a non-selected word line, a string selection line, a ground selection line, and a common source line.
Abstract translation: 目的：提供非易失性存储器件及其编程方法，以通过在编程操作中不同地设置用于自增强的偏置条件来防止未被选择的存储器单元被编程。 构成：存储单元阵列（110）包括多个存储单元。 控制逻辑单元（120）对多个存储器单元进行编程，并将多个程序循环分成两个程序循环区段。 控制逻辑单元在每个程序循环部分不同地设置用于自增强的偏置条件。 电压发生器（130）产生要施加到所选字线，未选择字线，串选择线，地选择线和公共源线的电压。
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公开(公告)号：KR1020170014645A
公开(公告)日：2017-02-08
申请号：KR1020150108354
申请日：2015-07-30
Applicant: 삼성전자주식회사 , 서울대학교산학협력단
Abstract: 리텐션에의한데이터손실을방지하기위한메모리영역을포함하는메모리장치의작동방법이공개된다. 상기방법은은 상기메모리영역에저장된데이터를제1리드전압을이용하여리드하고제1데이터를생성하는단계와, 상기메모리영역에저장된상기데이터를제2리드전압을이용하여리드하고제2데이터를생성하는단계와, 상기제1데이터와상기제2데이터를비교하고, 비교결과에따라변경된비트들을판별하고, 판별된비트들각각이리텐션복구비트인지손상된셀 비트인지를판단하는단계와, 상기판별된비트들중에서상기리텐션복구비트로판단된비트들을포함하는제3데이터를생성하는단계를포함한다. 상기제1리드전압과상기제2리드전압은서로동일하거나서로다를수 있다.
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公开(公告)号：KR1020150047394A
公开(公告)日：2015-05-04
申请号：KR1020130127421
申请日：2013-10-24
Applicant: 삼성전자주식회사
CPC classification number: G11C16/225 , G11C16/0483 , G11C16/10
Abstract: 본발명에따른저장장치의프로그램방법은: 메모리블록에적어도하나의오픈페이지가존재하는지를판별하는단계; 상기적어도하나의오픈페이지가존재할때, 더미패턴프로그램동작을통하여상기적어도하나의오픈페이지를클로징하는단계; 및상기메모리블록에이어쓰기를수행하는단계를포함한다.
Abstract translation: 根据本发明的存储设备包括以下步骤：确认在存储块处存在至少一个打开页面; 当存在至少一个打开的页面时，通过操作虚拟模式程序来关闭至少一个打开的页面; 并在存储器块中连续执行写入。
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