公开(公告)号：KR102086775B1

公开(公告)日：2020-03-09

申请号：KR1020130114689

申请日：2013-09-26

Applicant: 삼성전자주식회사

Inventor： 석종현 ,  김도형 ,  송원형 ,  이영호

IPC: G11C7/10 ,  G11C5/04 ,  G11C5/02

公开(公告)号：KR1020170068690A

公开(公告)日：2017-06-20

申请号：KR1020150175237

申请日：2015-12-09

Applicant: 삼성전자주식회사

Inventor： 권오성 ,  김진현 ,  송원형 ,  최지현

IPC: G11C11/406 ,  G11C11/408 ,  G11C5/04 ,  G11C5/12 ,  G11C8/12 ,  G11C8/06

CPC classification number: G06F12/00 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/02 ,  G11C5/04 ,  G11C7/1042 ,  G11C7/1057 ,  G11C8/12 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093 ,  G11C2207/2209

Abstract: 본발명은메모리모듈내에서랭크인터리빙동작을수행하는반도체메모리장치를개시한다. 반도체메모리장치는칩 내에형성된제1 메모리영역과상기칩과동일한칩 내에형성되고사용선택신호에따라상기제1 메모리영역과는독립적으로억세스되는제2 메모리영역을포함한다. 제1,2 메모리영역들은커맨드및 어드레스라인들을공유하고상기사용선택신호에따라랭크인터리빙동작을수행한다.

Abstract translation: 本发明公开了一种在存储器模块中执行秩交织操作的半导体存储器件。 的半导体存储器件包括被独立地访问第一存储区与所述芯片和根据形成在芯片中的所述第一存储区域中形成在相同的芯片选择信号的第二存储区。 第一和第二存储器区域共享命令和地址线并且根据使用选择信号执行秩交织操作。

公开(公告)号：KR1020150007188A

公开(公告)日：2015-01-20

申请号：KR1020130114689

申请日：2013-09-26

Applicant: 삼성전자주식회사

Inventor： 석종현 ,  김도형 ,  송원형 ,  이영호

IPC: G11C7/10 ,  G11C5/02 ,  G11C11/4093

CPC classification number: G11C7/10 ,  G11C5/025 ,  G11C5/04

Abstract: A memory module to improve data signal fidelity is disclosed. The memory module includes memory chips arranged on a printed circuit board; data buffers disposed on a first surface of the printed circuit board, and connected to the memory chips to correspond thereto, and resistance units disposed on a second surface opposite to the first surface of the printed circuit board, and connected to the data buffers to correspond thereto, wherein the resistance unit has a first terminal connected to a connecting terminal of the printed circuit board, and a second terminal connected to an input terminal of the data buffer through a first via hole passing through the printed circuit board, wherein an output terminal of the data buffer is connected to the memory chip through a signal line formed on an internal layer of the printed circuit board through a second via hole, and wherein the input terminal of the data buffer is disposed adjacent to the memory chip, and the output terminal of the data buffer is disposed adjacent to the connecting terminal.

Abstract translation: 公开了一种用于提高数据信号保真度的存储器模块。 存储器模块包括布置在印刷电路板上的存储芯片; 数据缓冲器，其布置在印刷电路板的第一表面上，并连接到与其对应的存储器芯片;以及电阻单元，设置在与印刷电路板的第一表面相对的第二表面上，并连接到数据缓冲器以对应 其中电阻单元具有连接到印刷电路板的连接端子的第一端子和通过穿过印刷电路板的第一通孔连接到数据缓冲器的输入端子的第二端子，其中输出端子 的数据缓冲器通过经由第二通孔形成在印刷电路板的内层上的信号线连接到存储器芯片，并且其中数据缓冲器的输入端子被布置为与存储器芯片相邻，并且输出端 数据缓冲器的端子设置成与连接端子相邻。

公开(公告)号：KR1020100103212A

公开(公告)日：2010-09-27

申请号：KR1020090021717

申请日：2009-03-13

Applicant: 삼성전자주식회사

Inventor： 송원형

IPC: G01R31/26 ,  H01L21/66 ,  G01R31/3183

CPC classification number: G01R31/3193 ,  G01R31/31917 ,  G01R31/31922

Abstract: PURPOSE: A test board and a test system including the same are provided to simultaneously test a plurality of devices to be tested using a plurality of test modules. CONSTITUTION: A clock generator(220) outputs an internal clock signal in response with a clock signal. A latch unit(210) outputs a first control signal, a data signal, and a second control signal. An error detecting unit(230) outputs the data signal of the latch unit to a device to be tested. The device is tested by comparing a data signal outputted from the device with the data signal of the latch signal. An error determination signal is outputted.

Abstract translation: 目的：提供一种测试板和包括该测试板的测试系统，以使用多个测试模块同时测试待测试的多个设备。 构成：响应于时钟信号，时钟发生器（220）输出内部时钟信号。 锁存单元（210）输出第一控制信号，数据信号和第二控制信号。 错误检测单元（230）将锁存单元的数据信号输出到要测试的设备。 通过将从器件输出的数据信号与锁存信号的数据信号进行比较来测试器件。 输出误差判定信号。