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公开(公告)号：KR20210034726A
公开(公告)日：2021-03-31
申请号：KR1020190116041A
申请日：2019-09-20
Applicant: 삼성전자주식회사
CPC classification number: G06F11/1068 , G06F11/1012 , G06F1/08 , G06F11/076 , G06F11/1016 , G06F11/1044 , G06F11/1072 , G06F11/1679 , G06F3/0619
Abstract: 본 발명에 따른 메모리 모듈은, 제 1 입출력 폭을 갖고, 데이터를 저장하는 제 1 메모리 칩들, 제 2 입출력 폭을 갖고, 상기 데이터의 에러를 정정하기 위한 에러 정정 코드를 저장하는 제 2 메모리 칩, 및 메모리 제어기로부터 클록, 명령어, 및 어드레스를 수신하고, 상기 제 1 메모리 칩들 및 상기 제 2 메모리 칩에 상기 클록, 상기 명령어, 및 상기 어드레스를 전송하는 드라이버 회로를 포함하고, 상기 제 1 메모리 칩들의 각각의 어드레스 뎁쓰와 상기 제 2 메모리 칩의 어드레스 뎁쓰는 서로 다른 것을 특징으로 한다.
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公开(公告)号：KR101851945B1
公开(公告)日：2018-04-26
申请号：KR1020110063585
申请日：2011-06-29
Applicant: 삼성전자주식회사
Inventor： 송원형
IPC: G01R31/303
CPC classification number: G01R31/31919 , G01R31/31908 , H01L2924/0002 , H01L2924/00
Abstract: 반도체모듈은복수의모듈핀들및 반도체장치를포함한다. 복수의모듈핀들은식별패턴신호의 M(M은자연수)비트들을각각출력한다. 반도체장치는복수의장치핀들을포함하고, 테스트제어신호에기초하여복수의모듈핀들과복수의장치핀들사이의연결관계를식별하기위한식별패턴신호를복수의장치핀들을통하여출력한다.
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公开(公告)号：KR1020120110877A
公开(公告)日：2012-10-10
申请号：KR1020110029042
申请日：2011-03-30
Applicant: 삼성전자주식회사
Inventor： 송원형
IPC: G11C11/4096 , G11C11/4093 , G11C11/4076 , G11C11/409
CPC classification number: G11C7/1096 , G11C7/1093 , G11C11/401 , G11C29/023 , G11C29/028 , G11C2207/2254
Abstract: PURPOSE: A method for accelerating a write timing calibration in a semiconductor memory device and a calibration accelerating circuit thereof are provided to minimize a boot-up timing by reduce write timing calibration time. CONSTITUTION: A write timing calibration accelerating circuit includes a phase difference detecting unit(210) and a detection data output unit(220). The phase difference detecting unit detects a phase difference between a first signal and a second signal applied for a write timing calibration. The detection data output unit outputs the detection data corresponding to the detected phase difference through a data output line. [Reference numerals] (100) Controller; (200) Memory device; (210) Phase difference detecting unit; (220) Detection data output unit; (230) Selecting unit; (235) DQ output unit; (240) Control unit; (250) Memory cell array
Abstract translation: 目的：提供一种用于加速半导体存储器件及其校准加速电路中的写入定时校准的方法，以通过减少写入定时校准时间来最小化启动定时。 构成：写时序校准加速电路包括相位差检测单元（210）和检测数据输出单元（220）。 相位差检测单元检测施加在写定时校准中的第一信号和第二信号之间的相位差。 检测数据输出单元通过数据输出线输出与检测出的相位差对应的检测数据。 （附图标记）（100）控制器; （200）存储设备; （210）相位差检测单元; （220）检测数据输出单元; （230）选择单位; （235）DQ输出单元; （240）控制单元; （250）存储单元阵列
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公开(公告)号：KR1020170054095A
公开(公告)日：2017-05-17
申请号：KR1020150156823
申请日：2015-11-09
Applicant: 삼성전자주식회사
IPC: G11C14/00 , G11C5/02 , G11C11/408 , G11C17/00
CPC classification number: G06F3/0635 , G06F3/0611 , G06F3/0673 , G06F13/1668 , G06F13/4068 , G06F17/5072 , G06F17/5077 , G11C5/025 , G11C7/1006 , G11C11/4096 , Y02D10/14 , Y02D10/151
Abstract: 반도체장치및 반도체시스템이제공된다. 반도체장치는, 메모리셀 어레이; 상기메모리셀 어레이를액세스하기위한제1 연산을수행하도록구현된제1 타입스탠다드셀 및상기제1 연산을수행하되상기제1 타입스탠다드셀과다른성능특성을갖는제2 타입스탠다드셀이배치된스탠다드셀 영역; 및상기스탠다드셀 영역에배치된스탠다드셀에대해배치및 배선(place and route) 작업을수행하는프로그램을포함하는 ROM(Read Only Memory)를포함한다.
Abstract translation: 提供了一种半导体器件和半导体系统。 一种半导体器件包括：存储单元阵列; 第一类标准单元被配置为执行用于访问存储器单元阵列的第一操作和具有第二类型标准单元的第二类型标准单元，该第二类型标准单元具有与第一类型标准单元不同的性能特征， 小区区域; 以及包括用于对布置在标准单元区域中的标准单元执行布局和布线操作的程序的ROM（只读存储器）。
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公开(公告)号：KR1020130002564A
公开(公告)日：2013-01-08
申请号：KR1020110063585
申请日：2011-06-29
Applicant: 삼성전자주식회사
Inventor： 송원형
IPC: G01R31/303
CPC classification number: G01R31/31919 , G01R31/31908 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor module and a test system using the same are provided to efficiently identify a pin connection relation inside the semiconductor module. CONSTITUTION: A semiconductor module(1000) is composed of multiple module pins(MP1,MP2-MPm) and a semiconductor device(1010). The multiple module pins output M bits of an identification pattern signal respectively. The semiconductor device includes multiple device pins, and outputs the identification pattern signal, which is to identify connection relations among the multiple device pins based on a test control signal, through the multiple device pins.
Abstract translation: 目的：提供半导体模块和使用其的测试系统以有效地识别半导体模块内的引脚连接关系。 构成：半导体模块（1000）由多个模块引脚（MP1，MP2-MPm）和半导体器件（1010）组成。 多个模块引脚分别输出识别图案信号的M位。 该半导体器件包括多个器件引脚，并且通过多个器件引脚输出识别图案信号，该标识图案信号是基于测试控制信号识别多个器件引脚之间的连接关系。
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Patent Agency Ranking
公开(公告)号：KR1020170066083A
公开(公告)日：2017-06-14
申请号：KR1020150172661
申请日：2015-12-04
Applicant: 삼성전자주식회사
Inventor： 송원형
IPC: G11C5/04 , G11C7/10 , H05K7/14 , H01L23/495
CPC classification number: G06F13/4068 , G06F1/185 , G06F3/0626 , G06F3/0656 , G06F3/0683 , G06F13/1673 , H01L24/17 , H01L24/29 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73207 , H01L2224/73253 , H01L2224/73265 , H01L2924/00014 , H01L2924/1434 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
Abstract: 메모리패키지, 확장가능한메모리모듈및 멀티-모듈메모리시스템이개시된다. 본개시의예시적실시예에따른확장메모리모듈이착탈가능한베이스메모리모듈은, 모듈보드, 모듈보드에부착되는제1 면및 제1 면에대향하는제2 면을가지는복수의메모리패키지들을포함할수 있다. 복수의메모리패키지들각각은, 확장메모리모듈과연결되도록메모리패키지의제2 면상에노출된복수의패키지단자들을포함할수 있다.
Abstract translation: 公开了一种存储器封装，可扩展存储器模块和多模块存储器系统。 扩展存储器模块是根据本公开的示例性实施例的可拆卸式底座存储器模块，可以包括具有面向所述第一表面和所述第一表面的第二表面被附接到所述模块基板的多个存储器封装，模块基板 有。 多个存储器封装中的每一个可以包括暴露在存储器封装的第二侧上用于与扩展存储器模块连接的多个封装端子。
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7.发明公开
公开(公告)号：KR1020160068305A
公开(公告)日：2016-06-15
申请号：KR1020140173816
申请日：2014-12-05
Applicant: 삼성전자주식회사
CPC classification number: G06F3/0638 , G06F3/0604 , G06F3/0629 , G06F3/0683 , G11C7/10 , G11C8/12 , G11C8/06 , G11C5/025 , G11C8/18 , G11C2029/1806
Abstract: 적층형메모리장치는, 어드레스리매핑회로및 복수의반도체다이(semiconductor die)를포함한다. 상기어드레스리매핑회로는복수의칩 선택신호들및 복수의칩 식별신호들을수신하기위한복수의입력단자들을포함하고, 상기입력단자들의일부에해당하는유효입력단자들을통하여상기칩 선택신호들및 상기칩 식별신호들의일부에해당하는입력신호들을수신하고, 상기입력신호들및 리매핑제어신호에기초하여복수의내부칩 선택신호들을발생한다. 상기복수의반도체다이들은상기내부칩 선택신호들을각각수신하는메모리장치들의각각을포함하고상하로적층된다. 주소관리방법에따라서최적화된어드레스리매핑기능을수행함으로써장치및 시스템의성능을향상시킬수 있다.
Abstract translation: 根据本发明的堆叠式存储装置包括地址重映射电路和多个半导体管芯。 地址重映射电路包括用于接收多个芯片选择信号和多个芯片识别信号的多个输入元件。 通过对应于一部分输入元件的有效输入元件，接收对应于芯片选择信号的一部分的输入信号和芯片识别信号，并且基于输入信号和重映射控制信号产生多个内部芯片选择信号。 每个半导体管芯包括接收内部芯片选择信号并垂直堆叠的存储器件。 通过执行根据地址管理方法优化的地址重映射功能，可以提高装置和系统的性能。
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公开(公告)号：KR1020140100752A
公开(公告)日：2014-08-18
申请号：KR1020130013878
申请日：2013-02-07
Applicant: 삼성전자주식회사
CPC classification number: G11C8/06 , G11C5/04 , G11C7/1045
Abstract: According to the present invention, a memory module includes a plurality of semiconductor memory devices. Each of the semiconductor memory devices includes a memory cell array which includes a plurality of memory cells arranged in a region where a plurality of bit lines and a plurality of word lines cross each other; a mode register set (MRS) circuit which generates an enable signal corresponding to an error generation mode for each of the semiconductor memory devices in response to an MRS command applied from a command decoder; and an address buffer which compares an address signal inputted from the outside with a prestored, predetermined address signal, based on the enable signal. When the address signal inputted from the outside is identical with the predetermined address signal, data other than data inputted from the outside is written to a memory cell corresponding to the predetermined address signal.
Abstract translation: 根据本发明，存储器模块包括多个半导体存储器件。 每个半导体存储器件包括存储单元阵列，该存储单元阵列包括布置在多个位线和多个字线交叉的区域中的多个存储单元; 模式寄存器组（MRS）电路，响应于从命令解码器施加的MRS命令，产生对应于每个半导体存储器件的误差产生模式的使能信号; 以及地址缓冲器，其根据使能信号将从外部输入的地址信号与预先存储的预定地址信号进行比较。 当从外部输入的地址信号与预定地址信号相同时，从外部输入的数据以外的数据被写入与预定地址信号对应的存储单元。
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公开(公告)号：KR1020140063366A
公开(公告)日：2014-05-27
申请号：KR1020130015898
申请日：2013-02-14
Applicant: 삼성전자주식회사
IPC: G11C5/02
Abstract: The present invention relates to a memory module. The memory module of the present invention comprises: a printed circuit board; first semiconductor packages provided on one surface of the printed circuit board; and second semiconductor packages provided on the other surface of the printed circuit board. The number of ranks formed by the first semiconductor packages is different from a number of ranks formed by the second semiconductor packages.
Abstract translation: 本发明涉及一种存储器模块。 本发明的存储器模块包括：印刷电路板; 设置在印刷电路板的一个表面上的第一半导体封装; 以及设置在印刷电路板的另一个表面上的第二半导体封装。 由第一半导体封装形成的等级的数量与由第二半导体封装形成的等级数不同。
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公开(公告)号：KR1020110138626A
公开(公告)日：2011-12-28
申请号：KR1020100058626
申请日：2010-06-21
Applicant: 삼성전자주식회사
Inventor： 송원형
CPC classification number: G11C5/00 , G11C5/04 , G11C29/26 , G11C2029/2602
Abstract: PURPOSE: A memory module mounting a parallel test device is provided to reduce test time by simultaneously testing a plurality of ranks. CONSTITUTION: A parallel test device(130,132) is a memory module with a plurality of ranks. Each rank generates the first parity data about write data composed of a plurality of bits and the first data replacing one or more bits with the first parity data in a writing operation and generates the second parity data about the first data in a reading operation, and transmits the second parity data as read data in response to a parallel test mode control signal. A parallel test controller(120,122) controls the writing and reading operations in the parallel test mode by generating a parallel test mode control signal.
Abstract translation: 目的：提供安装并行测试装置的内存模块，通过同时测试多个等级来减少测试时间。 构成：并行测试装置（130,132）是具有多个等级的存储器模块。 每个等级在写入操作中产生关于由多个比特组成的写入数据的第一奇偶校验数据和用第一奇偶校验数据替换一个或多个比特的第一数据，并且在读取操作中生成关于第一数据的第二奇偶校验数据，以及 响应于并行测试模式控制信号，将第二奇偶校验数据作为读数据发送。 并行测试控制器（120,122）通过产生并行测试模式控制信号来控制并行测试模式中的写入和读取操作。
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