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公开(公告)号：KR100132837B1
公开(公告)日：1998-04-16
申请号：KR1019940010488
申请日：1994-05-13
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: The capacitor manufacturing method is comprised of the step of forming an insulating layer(13) having an opening part(15) exposing an active area on a substrate(10) where a element separation region(12) is formed, the step of forming a first conducting layer(16') of a first dopping density which is connected to the active area(11) on the insulating layer(13), the step of depositing a conducting material of greater dopant density than the first conducting layer to form a second conducting layer(16), after that, the step of patterning the second conducting layer(16) and the first conducting layer(16') using a lithography process, whereby forming the storage electrode(16,16'), whose lower part is of low dopant desity and upper part is of high dopant density, and the step of forming a dielectric film(17) of the capacitor and a plate electrode(18) in succession on the storage electrode.
Abstract translation: 电容器制造方法包括形成绝缘层（13）的步骤，所述绝缘层（13）具有在基板（10）上暴露有源区域的开口部分（15），其中形成元件分离区域（12），形成 第一掺杂密度的第一导电层（16'），其连接到绝缘层（13）上的有源区（11）;沉积具有比第一导电层更大的掺杂剂密度的导电材料以形成第二导电层 （16），之后，使用光刻工艺对第二导电层（16）和第一导电层（16'）进行图案化的步骤，由此形成其下部为 低掺杂剂浓度和上部掺杂剂浓度高的步骤，以及在电容器上形成电介质膜（17）和在电极上连续形成平板电极（18）的步骤。
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公开(公告)号：KR1019970003893B1
公开(公告)日：1997-03-22
申请号：KR1019930022236
申请日：1993-10-25
Applicant: 삼성전자주식회사
IPC: H01L21/76
CPC classification number: H01L21/32
Abstract: The present invention relates to a method of isolating electrical elements for a semiconductor device to remove generation of bird's beak. The inventive method includes the steps of: forming a first oxide film on a semiconductor substrate; forming a silicon film on the first oxide film; forming an oxidation preventing film on the silicon film; performing a thermal treatment on a resultant in an ambient of nitric gas; etching a part of the oxidation preventing film to form an opening; forming a thermal oxide film by performing a thermal oxidation on the opening; and removing the oxidation preventing film.
Abstract translation: 本发明涉及隔离半导体器件的电气元件以消除鸟喙的产生的方法。 本发明的方法包括以下步骤：在半导体衬底上形成第一氧化膜; 在所述第一氧化物膜上形成硅膜; 在硅膜上形成氧化防止膜; 对硝酸气体的产生物进行热处理; 蚀刻氧化防止膜的一部分以形成开口; 通过对所述开口进行热氧化而形成热氧化膜; 并除去氧化防止膜。
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公开(公告)号：KR1019940009610B1
公开(公告)日：1994-10-15
申请号：KR1019910015243
申请日：1991-08-31
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: The method for fabricating a capacitor of a highly integrated semiconductor memory device includes the steps of: sequentially forming a first conductive layer, first material layer, second conductive layer and second material layer on a semiconductor substrate; forming a first storage electrode pattern on the second material layer; selectively etching the second material layer; second conductive layer and first material layer using the first storage electrode pattern as a mask; forming a third conductive layer on the overall surface of the substrate; forming a second storage electrode pattern on the resultant; selectively etching the materials placed on the first conductive layer using the second storage electrode pattern as an etch mask; forming a third storage electrode pattern on the resultant; and carrying out etch process using the third storage electrode pattern as an etch mask to form a storage electrode.
Abstract translation: 制造高度集成的半导体存储器件的电容器的方法包括以下步骤：在半导体衬底上依次形成第一导电层，第一材料层，第二导电层和第二材料层; 在所述第二材料层上形成第一存储电极图案; 选择性地蚀刻第二材料层; 第二导电层和使用第一存储电极图案作为掩模的第一材料层; 在所述基板的整个表面上形成第三导电层; 在所述结果上形成第二存储电极图案; 使用第二存储电极图案作为蚀刻掩模来选择性地蚀刻放置在第一导电层上的材料; 在所述结果上形成第三存储电极图案; 并且使用第三存储电极图案作为蚀刻掩模进行蚀刻处理以形成存储电极。
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公开(公告)号：KR1019940000503B1
公开(公告)日：1994-01-21
申请号：KR1019910005645
申请日：1991-04-09
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: The method comprises; (A) filling a trench (12) with the 1st insulating material after forming the 1st trench by etching the fixed device separation region of the 1st conduction type semiconductor substrate (10); (B) forming a gate (18) with a gate insulating layer on the surface of a trench separation region; (C), etching an insulating layer located between the fixed gates until the surface of the substrate (10) exposed and forming bit line (24) connecting with the exposed surface; (D) forming the 2nd shallower trench (30) than the depth of the trench separation region by aligning with photolithography of capacitor region close to each of the 1st trenches (12), (E) forming a dielectric layer (36) to wrap round the 1st conduction layer (34), and (F) forming the 2nd conduction layer (38) on the whole surface of the above substrate (10).
Abstract translation: 该方法包括： （A）通过蚀刻第一导电型半导体衬底（10）的固定器件分离区域形成第一沟槽之后，用第一绝缘材料填充沟槽（12）。 （B）在沟槽分离区域的表面上形成具有栅极绝缘层的栅极（18）; （C），蚀刻位于所述固定栅极之间的绝缘层，直到所述基板（10）的表面露出并且形成与所述暴露表面连接的位线（24）; （D）通过与形成介电层（36）的每个第一沟槽（12），（E）附近的电容器区域的光刻对准，与沟槽分离区域的深度相比，形成第二较浅沟槽（30） 第一导电层（34）和（F）在上述基板（10）的整个表面上形成第二导电层（38）。
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Patent Agency Ranking
公开(公告)号：KR1019930018695A
公开(公告)日：1993-09-22
申请号：KR1019920003264
申请日：1992-02-28
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 본 발명은 반도체장치의 제조방법에 관한 것으로 특히 접촉창형성을 위한 소정의 물질층을 형성하는 공정, 접촉창이 형성될 영역의 상기 소정의 물질층을 부분적으로 제거함으로써 요부를 형성하는 공정, 및 상기 요부측벽에 스페이서를 형성한 후에 계속해서 접촉창을 형성하는 공정을 제공한다. 따라서 최소피쳐사이즈 보다 더 작으면서도 신뢰성 있는 접촉장을 형성할 수 있어 다층배선의 신뢰도를 증가시킬 수 있다.
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公开(公告)号：KR1019930005218A
公开(公告)日：1993-03-23
申请号：KR1019910015243
申请日：1991-08-31
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: 내용 없음.
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18.发明公开
公开(公告)号：KR1019950034728A
公开(公告)日：1995-12-28
申请号：KR1019940010488
申请日：1994-05-13
Applicant: 삼성전자주식회사
IPC: H01L27/108
Abstract: 반도체장치의 커패시터 및 그 제조방법이 개시되어 있다. 반도체기판 상에 활성영역을 한정하기 위해 소자분리 영역이 형성되고 상기 소자분리 영역이 형성된 상기 기판 상에는 활성영역을 노출시키는 개구부를 갖는 절연층이 형성된다. 상기 절연층 상에는, 상기 개구부를 통해 상기 활성영역과 접속하는 제1도우핑 농도의 도판트를 갖는 제1도전층과, 상기 제1도전층 상에 형성된 상기 제1도우핑 농도보다 높은 제2도우핑 농도의 상기 도판트를 갖는 제2도전층으로 이루어진 커패시터의 제1전극이 형성된다. 상기 제1전극 상에는 커패시터의 유전체막 및 제2전극이 차례로 형성된다. 커패시터의 특성을 개선시키면서 분리 펀치쓰루우를 방지할 수 있다.
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公开(公告)号：KR100082508B1
公开(公告)日：1995-02-20
申请号：KR1019910015251
申请日：1991-08-31
Applicant: 삼성전자주식회사
IPC: H01L27/108
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公开(公告)号：KR100082506B1
公开(公告)日：1995-02-20
申请号：KR1019910015243
申请日：1991-08-31
Applicant: 삼성전자주식회사
IPC: H01L27/108
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