公开(公告)号：KR1020140112923A

公开(公告)日：2014-09-24

申请号：KR1020130027617

申请日：2013-03-15

Applicant: 삼성전자주식회사

Inventor： 장미정 ,  이기석 ,  최재복

IPC: H01L21/28 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, a trench is formed by partly removing the upper part of a substrate, thereby forming a protruding active region. A device isolation layer pattern structure which partly fills the trench is formed. An additional active layer is formed on the device isolation layer pattern structure and the active region part exposed by the trench. An additional active pattern is formed at the upper sidewall of the protruding active region by etching the additional active layer. Thereby, the contact margin of a part which is electrically connected to a capacitor can be secured, the probability of the misalignment of a contact hole can be reduced, and a semiconductor device having excellent operating characteristics can be manufactured.

Abstract translation: 在制造半导体器件的方法中，通过部分地去除衬底的上部而形成沟槽，由此形成突出的有源区。 形成部分填充沟槽的器件隔离层图案结构。 在器件隔离层图案结构和由沟槽露出的有源区域部分上形成附加的有源层。 通过蚀刻附加活性层，在突出的有源区的上侧壁处形成附加的有源图案。 由此，可以确保与电容器电连接的部分的接触余量，可以降低接触孔的未对准的可能性，并且可以制造具有优异的工作特性的半导体器件。

公开(公告)号：KR1020120139292A

公开(公告)日：2012-12-27

申请号：KR1020110059022

申请日：2011-06-17

Applicant: 삼성전자주식회사

Inventor： 한승욱 ,  최재복 ,  이동현 ,  전남호

IPC: H01L29/78 ,  H01L21/336

CPC classification number: G11C5/025 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1116 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/1033 ,  H01L29/4238

Abstract: PURPOSE: A semiconductor device is provided to improve reliability by maximizing the width of second impurity doping regions. CONSTITUTION: A driving circuit region includes a device isolation pattern, a gate electrode(120), a gate dielectric pattern, a first impurity doping region, and a driving transistor. A device isolation pattern defines an active part on a substrate. A gate electrode is arranged on the substrate and includes a closed loop type channel part(123). A gate dielectric pattern is arranged between the active part and the gate electrode. A first impurity doping region is arranged in the active part surrounded with the channel part and is separated from the device isolation pattern. A driving transistor is arranged in the active part outside the gate electrode and is separated from the first impurity doping region.

Abstract translation: 目的：提供半导体器件以通过最大化第二杂质掺杂区域的宽度来提高可靠性。 构成：驱动电路区域包括器件隔离图案，栅极电极（120），栅极电介质图案，第一杂质掺杂区域和驱动晶体管。 器件隔离图案定义衬底上的有源部分。 栅电极设置在基板上并且包括闭环型通道部分（123）。 在有源部分和栅电极之间布置有栅极电介质图案。 第一杂质掺杂区域布置在被沟道部分包围的有源部分中，并与器件隔离图案分离。 驱动晶体管布置在栅电极外部的有源部分中，并与第一杂质掺杂区分离。