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公开(公告)号：KR1020140091845A
公开(公告)日：2014-07-23
申请号：KR1020130003804
申请日：2013-01-14
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242
Abstract: The present invention includes a device isolation layer which is formed in a semiconductor substrate, a buried transistor electrode, an electrode mask on the buried transistor electrode, and an active region between the device isolation layer and the electrode mask on the buried transistor electrode. The upper part of the active region has an enlarged lateral surface which is made of a conductive material such as the active region. The active region which is metallized and enlarged by depositing the same conductive material as the active region on the upper part of the active region has a wide contact area between the active region and the DC. Therefore, a DC process can be easily carried out, and a DRAM semiconductor device with good electrical properties can be obtained.
Abstract translation: 本发明包括形成在半导体衬底中的器件隔离层，埋入晶体管电极，埋入晶体管电极上的电极掩模，以及器件隔离层和掩埋晶体管电极上的电极掩模之间的有源区。 有源区域的上部具有由诸如有源区域的导电材料制成的扩大的侧表面。 通过在有源区域的上部沉积与有源区相同的导电材料进行金属化和扩大的有源区域在有源区域和DC之间具有宽的接触面积。 因此，可以容易地进行DC工艺，可以获得具有良好电性能的DRAM半导体器件。
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公开(公告)号：KR1020130050160A
公开(公告)日：2013-05-15
申请号：KR1020110115364
申请日：2011-11-07
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L27/10876 , H01L29/42356 , H01L29/4236 , H01L29/66712
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to prevent a misalignment by self-aligning a part of a device isolation layer. CONSTITUTION: A structure of a mold layer(142) including opening parts is formed. A buried layer(152) is formed by filling the opening parts. The mold layer is removed. A spacer layer is formed on the outer sidewall of the buried layer. A device isolation trench(130T) is formed by etching a substrate.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过使器件隔离层的一部分自对准来防止错位。 构成：形成包括开口部的模具层（142）的结构。 通过填充开口部分形成掩埋层（152）。 去除模具层。 在掩埋层的外侧壁上形成间隔层。 通过蚀刻衬底形成器件隔离沟槽（130T）。
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公开(公告)号：KR101929478B1
公开(公告)日：2018-12-14
申请号：KR1020120045696
申请日：2012-04-30
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78 , H01L21/8239 , H01L27/105
Abstract: 기판 내에 형성된 제1 필드 영역, 상기 제1 필드 영역은 제1 필드 트렌치 및 상기 제1 필드 트렌치를 채우는 제1 필드 절연물을 포함하고, 상기 제1 필드 영역과 교차하고 서로 평행하게 연장하는 제2 필드 영역 및 게이트 구조체, 상기 제2 필드 영역은 제2 필드 트렌치 및 상기 제2 필드 트렌치를 채우는 제2 필드 절연물을 포함하고, 및 상기 게이트 구조체는 게이트 트렌치 및 상기 게이트 트렌치를 채우는 게이트 캡핑층을 포함하고, 및 상기 제1 필드 영역 상에 형성된 절연층을 포함하되, 상기 제2 필드 절연물의 상부 표면, 상기 게이트 캡핑층의 상부 표면, 및 상기 절연층의 상부 표면이 동일한 레벨에 위치하는 반도체 소자가 설명된다.
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公开(公告)号：KR101857729B1
公开(公告)日：2018-06-20
申请号：KR1020110059022
申请日：2011-06-17
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: G11C5/025 , H01L27/0207 , H01L27/088 , H01L27/1052 , H01L27/10873 , H01L27/10882 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L27/1116 , H01L27/11526 , H01L27/11573 , H01L29/1033 , H01L29/4238
Abstract: 반도체장치가제공된다. 본발명에따른반도체장치는셀 영역및 구동회로영역을포함할수 있다. 상기구동회로영역은, 기판내에활성부를정의하는소자분리패턴, 상기기판상에배치되고, 폐루프형태의채널부를포함하는게이트전극, 상기활성부및 게이트전극사이에배치되는게이트유전패턴, 평면적관점에서상기채널부로둘러싸인활성부내에배치되고, 상기소자분리패턴과이격되는제1 불순물도핑영역및 평면적관점에서상기게이트전극의외부의활성부내에배치되고상기제1 불순물도핑영역과이격되는제2 불순물도핑영역을포함하는구동트랜지스터를포함할수 있다.
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Patent Agency Ranking
公开(公告)号：KR101974350B1
公开(公告)日：2019-05-02
申请号：KR1020120119918
申请日：2012-10-26
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242 , H01L21/28
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公开(公告)号：KR1020130110733A
公开(公告)日：2013-10-10
申请号：KR1020120032928
申请日：2012-03-30
Applicant: 삼성전자주식회사
IPC: H01L21/027 , H01L21/28
CPC classification number: H01L23/5283 , H01L21/3086 , H01L21/76224 , H01L27/10891 , H01L29/0649 , H01L2924/0002 , H01L21/0274 , H01L21/28123 , H01L2924/00
Abstract: PURPOSE: A semiconductor device manufacturing method and a semiconductor device formed by the same prevent the misalignment of a mask by removing active lines with a self-alignment manner using a first mask pattern as an etching mask. CONSTITUTION: A first groove is extended in a first direction (D1) by pattering a substrate (1). An active line (1a) protruding from the substrate is formed. A first element separation film (3) filled in the first grooves is formed. A first mask pattern (5) in a line shape is extended in a second direction (D2) on the substrate. Multiple second grooves are formed by etching the first element separation film and the active line. Active parts are formed in the first direction. A first hole (17) is formed between the active parts. A second element separation film filled in a part of the first hole is formed.
Abstract translation: 目的：通过使用第一掩模图案作为蚀刻掩模，通过以自对准方式去除有源线来防止掩模的未对准而形成的半导体器件制造方法和半导体器件。 构成：通过图案化基板（1），第一凹槽沿第一方向（D1）延伸。 形成从基板突出的有源线（1a）。 形成填充在第一槽中的第一元件分离膜（3）。 线状的第一掩模图案（5）沿基板的第二方向（D2）延伸。 通过蚀刻第一元件分离膜和有源线来形成多个第二槽。 有源部分沿第一方向形成。 在活动部件之间形成第一孔（17）。 形成了填充在第一孔的一部分中的第二元件分离膜。
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公开(公告)号：KR1020140053685A
公开(公告)日：2014-05-08
申请号：KR1020120119918
申请日：2012-10-26
Applicant: 삼성전자주식회사
IPC: H01L27/108 , H01L21/8242 , H01L21/28
CPC classification number: H01L23/49838 , H01L27/0207 , H01L27/10814 , H01L27/10847 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L2924/0002 , H01L2924/00
Abstract: In the present invention, a plurality of parallel-trenches and a plurality of intersect-trenches are disposed to be in parallel on a semiconductor substrate. A plurality of active regions are confined on the semiconductor substrate by the parallel-trenches and the intersect-trenches. A plurality of lower conductive lines are disposed to traverse the active regions. A plurality of upper conductive lines are disposed to be parallel to each other, intersect the lower conductive lines, and traverse the active regions. Data storage elements are disposed to be connected to the active regions. Each of the parallel-trenches and the intersect-trenches is configured as a straight line. The parallel-trenches intersect the upper conductive lines and are at a first acute angle with respect to the upper conductive lines. The intersect-trenches intersect the parallel-trenches, and the parallel-trenches and the intersect-trenches are at a second acute angle.
Abstract translation: 在本发明中，多个平行沟槽和多个交叉沟槽在半导体衬底上平行设置。 多个有源区域通过平行沟槽和交叉沟槽限制在半导体衬底上。 布置多个下导电线以横越有源区。 多个上导线被设置为彼此平行，与下导电线相交，并且穿过有源区。 数据存储元件设置成连接到有源区域。 平行沟槽和交叉沟槽中的每一个被配置为直线。 平行沟槽与上导线相交并且相对于上导线处于第一锐角。 交叉沟槽与平行沟槽相交，平行沟槽和交叉沟槽处于第二锐角。
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公开(公告)号：KR1020130122399A
公开(公告)日：2013-11-07
申请号：KR1020120045696
申请日：2012-04-30
Applicant: 삼성전자주식회사
IPC: H01L21/336 , H01L29/78 , H01L21/8239 , H01L27/105
CPC classification number: H01L29/42312 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L29/4236 , H01L29/66621 , H01L21/76224
Abstract: Described is a semiconductor device which includes a first field region which is formed on a substrate and includes a first field trench and a first field insulation material which fills the first field trench, a second field region which crosses the first field region and is extended in parallel, and a gate structure. The second field region includes a second field trench and a second field insulation material which fills the second field trench. The gate structure includes a gate trench, a gate capping layer which fills the gate trench, and an insulation layer which is formed on the first field region. The upper surfaces of the second field insulation material, the gate capping layer, and the insulation layer are located on the same level.
Abstract translation: 描述了一种半导体器件，其包括第一场区，其形成在衬底上并且包括第一场沟槽和填充第一场沟的第一场绝缘材料，与第一场区交叉并延伸的第二场区 平行和门结构。 第二场区域包括填充第二场沟槽的第二场沟槽和第二场绝缘材料。 栅极结构包括栅极沟槽，填充栅极沟槽的栅极覆盖层和形成在第一场区上的绝缘层。 第二场绝缘材料，栅极覆盖层和绝缘层的上表面位于同一水平面上。
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公开(公告)号：KR100854501B1
公开(公告)日：2008-08-26
申请号：KR1020070018443
申请日：2007-02-23
Applicant: 삼성전자주식회사
Inventor： 최재복
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/4236 , H01L29/1054 , H01L29/66621 , H01L29/1037
Abstract: A MOS transistor having a recess channel region is provided to form a MOS transistor with a recess channel region and an improved current characteristic by forming a semiconductor region with a high carrier mobility characteristic in the recess channel region. A source region(107s) and a drain region(107d) are formed in an active region(105a) of a semiconductor substrate(100), separated from each other. A gate trench structure(133) is formed in the active region between the source region and the drain region. A gate electrode is formed in the gate trench structure. A gate dielectric layer is interposed between the gate trench structure and the gate electrode. A semiconductor region(140) is formed between the gate trench structure and the gate dielectric layer, including a different material from that of the active region. The gate trench structure can include an upper gate trench(115) crossing the active region and a lower gate trench(125) formed under the upper gate trench wherein the lower gate trench has a greater width than the upper gate trench.
Abstract translation: 提供具有凹槽沟道区域的MOS晶体管，以通过在凹槽沟道区域中形成具有高载流子迁移特性的半导体区域形成具有凹槽沟道区域和改进的电流特性的MOS晶体管。 在半导体衬底（100）的有源区（105a）中形成源区（107s）和漏区（107d），彼此分离。 在源极区域和漏极区域之间的有源区域中形成栅极沟槽结构（133）。 在栅极沟槽结构中形成栅电极。 栅极介电层插入在栅极沟槽结构和栅电极之间。 半导体区域（140）形成在栅极沟槽结构和栅极电介质层之间，包括与活性区域不同的材料。 栅极沟槽结构可以包括与有源区交叉的上栅极沟槽（115）和形成在上栅极沟槽下方的下栅极沟槽（125），其中下栅极沟槽具有比上栅极沟槽更大的宽度。
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