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公开(公告)号：KR100905202B1
公开(公告)日：2009-06-26
申请号：KR1020070088868
申请日：2007-09-03
Applicant: 성균관대학교산학협력단
IPC: H03F1/07
CPC classification number: H03F1/0288 , H03F1/0261 , H03F1/3205 , H03F1/56 , H03F3/601 , H03F2200/387 , H03F2200/391 , H03F2200/423 , H03F2200/451
Abstract: 본 발명은 도허티 증폭기 출력단 구성에 관한 것으로, 주 증폭부(carrier amplifier)와 보조 증폭부(peaking amplifier) 그리고 두 증폭부를 연결하는 콤팩트 λ/4 라인을 포함하는 것을 특징으로 한다.
두 증폭부를 연결하는 콤팩트 λ/4 라인은 상기 주 증폭부와 연결되어 병렬로 접지되는 제1 병렬 커패시터와; 상기 보조 증폭부와 연결되어 병렬로 접지되는 제2 병렬 커패시터와; 상기 주 증폭부와 상기 보조 증폭부를 연결하는 인덕터 또는 마이크로스트립 트랜스미션 라인을 포함한다. 그리고 본 발명에 따른 도허티 증폭기는 상기 주 증폭부와 상기 보조 증폭부를 연결하여 최종 출력으로 연결하는 매칭 네트워크 단과; 상기 주 증폭부와 상기 보조 증폭부의 전원입력으로 사용되는 λ/4 라인을 더 포함한다.
이에 의하여, 회로의 크기를 감소시키고 구조를 간략화 하면서도 증폭기의 선형성 및 고 효율을 유지할 수 있다.-
公开(公告)号：KR100858662B1
公开(公告)日：2008-09-16
申请号：KR1020070036966
申请日：2007-04-16
Applicant: (주)카이로넷 , 성균관대학교산학협력단
IPC: H01P5/12
CPC classification number: H01P5/12 , H03H7/0115 , H03H7/38
Abstract: A hybrid power divider is provided to reduce loss by equalizing resistance of an equivalent resistor to the resistance of an isolation resistor. A hybrid power divider includes an input port(210), a first output port(220), a second output port(230), an isolation port(240), and a dividing unit(250). The input port receives a wireless signal. The first output port transmits a first output signal branched from the inputted wireless signal to the outside. The second output port transmits a second output signal branched from the inputted wireless signal to the outside. The separation port balances the wireless signal. The dividing unit is connected to the input port at a first node, divides the wireless signal into the first and second output signals, the first output port at a second node, the second output port at a third node, and the separation port at a fourth node.
Abstract translation: 提供了一种混合功率分配器，通过使等效电阻器的电阻与隔离电阻的电阻相等来减少损耗。 混合功率分配器包括输入端口（210），第一输出端口（220），第二输出端口（230），隔离端口（240）和分隔单元（250）。 输入端口接收无线信号。 第一输出端口将从输入的无线信号分支的第一输出信号发送到外部。 第二输出端口将从输入的无线信号分支的第二输出信号发送到外部。 分离端口平衡无线信号。 分割单元在第一节点处连接到输入端口，将无线信号分成第一和第二输出信号，第二节点处的第一输出端口，第三节点处的第二输出端口，以及分离单元的分离端口 第四节点。
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公开(公告)号：KR101025375B1
公开(公告)日：2011-03-28
申请号：KR1020090125836
申请日：2009-12-17
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A method for writing data for a non-volatile memory storage is provided to minimize the use of an external buffer and a bus. CONSTITUTION: A memory chip in which a page having the same logic page number with a current page to be recorded is recorded is searched(410). It is determined whether the current page is able to be recorded to the memory chip in which the page having the same logic page number with a current page to be recorded is recorded or not(430). It is saved in the memory chip in which the page in which the current page has the same logical page number as described above is saved(440).
Abstract translation: 目的：提供用于写入非易失性存储器存储器的数据的方法，以最小化外部缓冲器和总线的使用。 构成：搜索具有与要记录的当前页面相同的逻辑页码的页面的存储器芯片（410）。 确定当前页面是否能够记录到具有与要记录的当前页面具有相同逻辑页码的页面的存储器芯片（430）。 保存在存储芯片中，其中当前页面具有与上述相同的逻辑页码的页面被保存（440）。
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公开(公告)号：KR100988388B1
公开(公告)日：2010-10-18
申请号：KR1020090034058
申请日：2009-04-20
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A method for improving performance of flash memory device and a flash memory device performing the same are provided to improve a processing speed and durability by reducing unnecessary recordings. CONSTITUTION: A buffer(120) stores data offered from a host device. In case the usage amount of the buffer excesses a certain level, a controller(130) selects sacrifice superblock based on the size and data access time of the updated data among logical superblocks saved in the buffer. The controller mixes data updated from the sacrifice superblocks, reconstructs to the sacrifice superblocks, and supplies the sacrifice superblocks through plural channels.
Abstract translation: 目的：提供一种用于提高闪存设备性能的方法和执行闪存设备的闪存设备，以通过减少不必要的记录来提高处理速度和耐久性。 构成：缓冲器（120）存储从主机设备提供的数据。 在缓冲器的使用量超过一定水平的情况下，控制器（130）基于保存在缓冲器中的逻辑超级块之间的更新数据的大小和数据访问时间来选择牺牲超级块。 控制器将从牺牲超级块更新的数据混合，重建到牺牲超级块，并通过多个通道提供牺牲超级块。
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公开(公告)号：KR1020090023814A
公开(公告)日：2009-03-06
申请号：KR1020070088868
申请日：2007-09-03
Applicant: 성균관대학교산학협력단
IPC: H03F1/07
CPC classification number: H03F1/0288 , H03F1/0261 , H03F1/3205 , H03F1/56 , H03F3/601 , H03F2200/387 , H03F2200/391 , H03F2200/423 , H03F2200/451
Abstract: A Doherty amplifier is provided to improve efficiency by using a different bias in a main amplifier and an auxiliary amplifier. A Doherty amplifier includes a first parallel capacitor(31), a second parallel capacitor(32), a transmission line unit(33b), and a matching network unit(35). A first parallel capacitor is connected in parallel to a main amplifier(10). The second parallel capacitor is connected in parallel to an auxiliary amplifier(20). The first and second parallel capacitors are grounded. The transmission line unit connects the main amplifier and the auxiliary amplifier. The transmission line unit is one of an inductor and a microstrip transmission line. The matching network unit is diverged between the second parallel capacitor and the transmission line unit.
Abstract translation: 提供了Doherty放大器，通过在主放大器和辅助放大器中使用不同的偏置来提高效率。 多赫蒂放大器包括第一并联电容器（31），第二并联电容器（32），传输线单元（33b）和匹配网络单元（35）。 第一并联电容器并联连接到主放大器（10）。 第二并联电容器并联连接到辅助放大器（20）。 第一和第二并联电容器接地。 传输线单元连接主放大器和辅助放大器。 传输线单元是电感器和微带传输线之一。 匹配网络单元在第二并联电容器和传输线单元之间发散。
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Patent Agency Ranking
公开(公告)号：KR1020090071834A
公开(公告)日：2009-07-02
申请号：KR1020070139752
申请日：2007-12-28
Applicant: 성균관대학교산학협력단
IPC: H03F1/07
CPC classification number: H03F1/0288 , H03F1/56 , H03F3/604 , H03F2200/15 , H03F2200/387 , H03F2200/451 , H03H7/38
Abstract: A Doherty amplifier is provided to improve efficiency while maintaining linearity by tuning output harmonic impedance of a carrier amplifier and a peak amplifier. A carrier amplifier performs the amplification operation of a signal regardless of the input signal level. A peak amplifier performs an amplification operation from a high power output when the input signal level is above the predetermined level. An output synthesizing circuit synthesizes and outputs the output of the carrier amplifier and the peak amplifier. An input branch circuit distributes the input signal to the carrier amplifier and the peak amplifier. A carrier amplifier output harmonic impedance tuning net(HTC) is installed in a rear part of the carrier amplifier and tunes the output harmonic impedance of the carrier amplifier. A peak amplifier output harmonic impedance tuning net is installed in the rear part of the peak amplifier and tunes the output harmonic impedance.
Abstract translation: 提供Doherty放大器以通过调整载波放大器和峰值放大器的输出谐波阻抗来提高效率，同时保持线性度。 无论输入信号电平如何，载波放大器执行信号的放大操作。 当输入信号电平高于预定电平时，峰值放大器从高功率输出执行放大操作。 输出合成电路合成并输出载波放大器和峰值放大器的输出。 输入分支电路将输入信号分配给载波放大器和峰值放大器。 载波放大器输出谐波阻抗调谐网（HTC）安装在载波放大器的后部，并调谐载波放大器的输出谐波阻抗。 峰值放大器输出谐波阻抗调谐网安装在峰值放大器的后部，并调谐输出谐波阻抗。
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公开(公告)号：KR101826047B1
公开(公告)日：2018-02-07
申请号：KR1020110098462
申请日：2011-09-28
Applicant: 삼성전자주식회사
IPC: G06F12/06
CPC classification number: G06F3/0608 , G06F3/0641 , G06F3/0679 , G06F12/0253
Abstract: 저장장치및 그구동방법이제공된다. 상기저장장치는서로다른물리어드레스에대응되는제1 및제2 저장영역을포함하고, 상기제1 저장영역내에제1 데이터가저장되는데이터저장부, 상기제1 데이터의공유량(reference count)를저장하는제1 메모리, 및상기제1 데이터의공유량이변화함에따라, 상기제1 데이터를상기제1 저장영역에서제2 저장영역으로재배치하는제어기를포함한다.
Abstract translation: 提供了一种存储设备及其驱动方法。 其中，存储设备包括与不同物理地址对应的第一存储区域和第二存储区域;数据存储器，用于存储第一存储区域中的第一数据;存储区域，用于存储第一数据的引用计数; 以及用于随着第一数据的共享量改变而将第一数据从第一存储区域重新定位到第二存储区域的控制器。
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