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公开(公告)号：KR101478258B1
公开(公告)日：2014-12-31
申请号：KR1020130051445
申请日：2013-05-07
Applicant: 숭실대학교산학협력단
IPC: G06T7/00
Abstract: 입력된영상에서차선경계선을인식한뒤 ROI를경계선주변으로제한하여연산량을줄이는차선인식방법및 그시스템을제공한다. 차선인식시스템은차선경계선을포함하는영상프레임을획득하는영상정보획득장치와, 차선경계선의기울기정보에따라상기차선경계선을인식하기위한Λ-ROI(Λ-shape Region Of Interest)를설정하는관심영역설정부및 Λ-ROI 영역내에서차선을인식하는차선인식부를포함하므로, 차선인식을위한연산량을줄일수 있다.
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公开(公告)号：KR101435008B1
公开(公告)日：2014-08-28
申请号：KR1020120141253
申请日：2012-12-06
Applicant: 숭실대학교산학협력단 , 건국대학교 산학협력단
IPC: G06F1/16
Abstract: 본 발명은 웨어러블 컴퓨터 및 상기 웨어러블 컴퓨터의 전도성 섬유와 전자 모듈의 연결 방법을 개시한다. 본 발명에 따르면, 전자 모듈을 포함하는 웨어러블 컴퓨터로서, 상기 전자 모듈에 연결되며 상기 전자 모듈 측으로 원형 고리 부분을 갖는 금속선; 및 상기 원형 고리의 소정 지점에서부터 상기 금속선과 나선형으로 교대로 배치되면서 꼬인 형태로 결합되는 전도성 섬유를 포함하는 웨어러블 컴퓨터가 제공된다. 본 발명에 따르면 금속선과 전도성 섬유를 안정적으로 결합시키며 연결 부분의 손상을 방지할 수 있는 장점이 있다.
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13.发明公开
公开(公告)号：KR1020140058455A
公开(公告)日：2014-05-14
申请号：KR1020140030111
申请日：2014-03-14
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
CPC classification number: Y02D10/13 , Y02D10/14 , Y02D10/151 , G06F13/1673 , G06F2213/0038
Abstract: A memory control apparatus for adaptively determining the order of execution of multiple memory access requests is disclosed. A memory access request buffer unit processes multiple memory access requests in an input order thereof, based on the input order and the bank and row information of memory addresses extracted from the memory access requests, but determines and stores a memory access request order such that memory access requests for the same bank and the same row are consecutively processed. A memory access request controller reads the memory access requests in the order determined by the memory access request buffer unit, distributes the memory access requests to banks, transmits, to a memory, the memory access requests distributed to the banks in order, and executes the memory access requests. A bank controller stores the memory access requests distributed to the banks in a buffer unit for each bank within a preset number, and controls an operational status for each bank. The memory access request controller checks whether the buffer unit for each bank is empty when distributing the memory access requests to the banks, and first transmits, to an empty buffer unit for each bank, even a memory access request which is in a back order in the memory access request buffer unit. According to the present invention, waiting times can be reduced by arranging multiple memory access requests, and power consumption can be reduced by making the best use of bandwidth.
Abstract translation: 公开了一种用于自适应地确定多个存储器访问请求的执行顺序的存储器控制装置。 存储器访问请求缓冲器单元基于从存储器访问请求提取的存储器地址的输入顺序和存储体和行信息来处理其输入顺序的多个存储器访问请求，但是确定并存储存储器访问请求顺序，使得存储器 对同一行和同一行的访问请求被连续处理。 存储器访问请求控制器以由存储器访问请求缓冲器单元确定的顺序读取存储器访问请求，向存储器分配存储器访问请求，向存储器依次发送分配给存储体的存储器访问请求，并执行 内存访问请求 银行控制器将分配给银行的存储器访问请求以预定数量存储在每个银行的缓冲单元中，并且控制每个银行的操作状态。 存储器访问请求控制器在向存储体分配存储器访问请求时检查每个存储体的缓冲器单元是否为空，并且首先向每个存储体的空缓冲器单元发送甚至是处于后续顺序的存储器访问请求 存储器访问请求缓冲器单元。 根据本发明，可以通过设置多个存储器访问请求来减少等待时间，并且可以通过充分利用带宽来降低功耗。
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14.发明公开
公开(公告)号：KR1020130075139A
公开(公告)日：2013-07-05
申请号：KR1020110143376
申请日：2011-12-27
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
CPC classification number: G06F12/00 , G06F13/1621 , G06F13/1631 , Y02D10/14
Abstract: PURPOSE: A method for controlling a semiconductor chip and a memory, and a recording medium in which a program to execute the method in a computer is recorded are provided to reduce waiting time, by arranging memory access requests. CONSTITUTION: A storing part (120) stores present processing target memory access request requesting access to a memory and memory access requests inputted before the present processing target memory request according to the input sequence. A control part (130) processes the present processing target memory access request and the prior memory access requests according to the input sequence, and processes memory access request for the same bank and the same row continuously. The control part includes an analysis part and an arrangement part. The analysis part analyzes memory address of the memory access requests to access. [Reference numerals] (120) Storing part; (130) Control part
Abstract translation: 目的：提供一种用于控制半导体芯片和存储器的方法以及记录有计算机执行方法的程序的记录介质，以通过布置存储器访问请求来减少等待时间。 构成：根据输入序列，存储部（120）存储请求对存储器的访问的当前处理对象存储器访问请求和在本处理目标存储器请求之前输入的存储器访问请求。 控制部（130）根据输入序列处理当前的处理目标存储器访问请求和先前的存储器访问请求，并且连续地处理同一个存储体和同一行的存储器访问请求。 控制部包括分析部和配置部。 分析部分分析存储器访问请求的存储器地址。 （附图标记）（120）存储部; （130）控制部分
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公开(公告)号：KR102260820B1
公开(公告)日：2021-06-07
申请号：KR1020190082020
申请日：2019-07-08
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
IPC: G06F13/26
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Patent Agency Ranking
公开(公告)号：KR102260819B1
公开(公告)日：2021-06-07
申请号：KR1020190082019
申请日：2019-07-08
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
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公开(公告)号：KR101885033B1
公开(公告)日：2018-08-02
申请号：KR1020170090314
申请日：2017-07-17
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
Abstract: 본발명은디지털클록데이터복원장치에관한것으로서, 입력신호가복수의지연셀을순차적으로통과하는동안, DCO 클록신호를이용하여각 지연셀에서상기입력신호의상승에지및 하강에지를검출하고, 상기상승에지및 하강에지의위치를카운팅한 카운트신호를생성하며, 상기입력신호가상기 DCO 클록신호에따라샘플링된 샘플링데이터를출력하는지연선로위상주파수검출기, 상기카운트신호와기 설정된매개변수를이용하여 DCO 클록신호의주파수를제어하기위한 DCO 제어신호를생성하는디지털루프필터, 상기 DCO 제어신호에따라출력주파수를조절하여상기 DCO 클록신호를생성하는디지털제어발진기, 기설정된기준인자에따라상기 DCO 클록신호의주파수를변환하는프로그래머블분주기, 상기 DCO 클록신호를이용하여복수의샘플링데이터를저장하고, 상기복수의샘플링데이터를기 저장된프리앰블과비교하여분주율을생성하는분주인자생성기, 그리고상기분주율에따라상기 DCO 클록신호를분주하여복원클록신호를출력하는클록분주기를포함한다. 이와같이본 발명에따르면, 클럭데이터복원장치의전체구성을디지털회로로구현하므로다른공정기술로의이식성이뛰어나고동작조건이유연하다는장점이있다.
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公开(公告)号：KR1020140014974A
公开(公告)日：2014-02-06
申请号：KR1020120082477
申请日：2012-07-27
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
CPC classification number: G11C7/22 , G06F13/1668 , G11C7/20 , G11C2207/2272
Abstract: An apparatus and method for controlling a memory are disclosed. A control clock generation unit generates at least one control clock transmitted together when data is transmitted to and received from a memory. A memory interface unit writes the data in the memory or reads the data from the memory. A memory control unit detects an estimated time when specific data is read by comparing the specific data with data read at each estimated time, with respect to at least one estimated time preset to read the specific data in correspondence with the control clock when reading the preset specific data from the memory. A system initialization unit computes a delay time delayed in reading the specific time by comparing the detected estimated time with time when the specific data is transmitted from the memory, and reads data at an optimum time obtained by adding the computed delay time to the time when the data is transmitted from the memory. According to the present invention, a communication delay between a controller and the memory is solved by newly setting a delay time during initialization even when configuring a new system in a PCB. The present invention can also be used in a high speed SRAM, DRAM, and flash memory, and realized by minimum additional logic by utilizing an internal clock and register. [Reference numerals] (110) Control clock generation unit; (120) Memory interface unit; (130) Memory control unit; (140) System initialization unit
Abstract translation: 公开了一种用于控制存储器的装置和方法。 当数据被发送到存储器并从存储器接收数据时，控制时钟产生单元产生一起发送的至少一个控制时钟。 存储器接口单元将数据写入存储器或从存储器读取数据。 存储器控制单元通过比较特定数据与每个估计时间读取的数据相对于预先设定的至少一个估计时间来检测特定数据的估计时间，以在读取预设时与控制时钟对应地读取特定数据 来自内存的特定数据。 系统初始化单元通过将检测到的估计时间与从存储器发送特定数据的时间进行比较来计算在读取特定时间时延迟的延迟时间，并且通过将所计算的延迟时间与计算出的延迟时间相加而获得的最佳时间读取数据， 从存储器发送数据。 根据本发明，即使在PCB中配置新的系统时，也通过新设定初始化时的延迟时间来解决控制器与存储器之间的通信延迟。 本发明还可以用于高速SRAM，DRAM和闪速存储器中，并且通过利用内部时钟和寄存器通过最小的附加逻辑实现。 （附图标记）（110）控制时钟生成单元; （120）存储器接口单元; （130）存储控制单元; （140）系统初始化单元
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公开(公告)号：KR101335367B1
公开(公告)日：2013-12-02
申请号：KR1020120043727
申请日：2012-04-26
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
CPC classification number: G11C8/12 , G11C8/06 , G11C8/08 , G11C11/408
Abstract: 메모리 제어 장치 및 방법이 개시된다. 본 발명은, 데이터를 복수의 뱅크에 순차적으로 분산 저장하고, 뱅크 정보와 행 정보의 일부를 서로 바꾼 행 주소 정보를 기초로 해당 데이터를 메모리에 쓰거나 메모리에서 해당 데이터를 읽는다. 본 발명에 따르면, 메모리에 접근할 때 행 바꿈이 일어나면 같은 뱅크가 아닌 다른 뱅크를 접근하도록 하여 대기 사이클 없이 블록 데이터를 읽거나 쓸 수 있고, 메모리 제어 장치 내부에서 간단한 주소 변환으로 가능하여 낮은 복잡도로 구현할 수 있다.
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公开(公告)号：KR1020130120666A
公开(公告)日：2013-11-05
申请号：KR1020120043727
申请日：2012-04-26
Applicant: 숭실대학교산학협력단
Inventor： 이찬호
CPC classification number: G11C8/12 , G11C8/06 , G11C8/08 , G11C11/408
Abstract: Disclosed are a device and a method for controlling a memory. The present invention sequentially distributes and stores data in a plurality of banks, and writes corresponding data in a memory or reads the corresponding data from the memory based on row address information generated through translation between the parts of row information and bank information. According to the present invention, a user may read or write block data without a standby cycle by accessing another bank, not the same bank, if the change of a row is generated when accessing a memory, and realize the invention with low complexity by achieving the memory control through simple address translation within the memory control device. [Reference numerals] (AA) Start;(BB) End;(S410) Receive request for memory access;(S430) Obtain conversion row address by changing part of bank information and row information in original row information;(S450) Write or read data corresponding to original row information in data through conversion row address information
Abstract translation: 公开了一种用于控制存储器的装置和方法。 本发明顺序地将数据分发并存储在多个存储体中，并且将对应的数据写入存储器中，或者根据行信息和存储体信息的部分之间的转换产生的行地址信息从存储器读取相应的数据。 根据本发明，如果在访问存储器时产生行的变化，则用户可以通过访问另一个存储体而不是相同的存储体来读取或写入没有备用周期的块数据，并且通过实现低的复杂度实现本发明 内存控制通过内存控制设备内的简单地址转换。 （AA）开始;（BB）结束;（S410）存储器访问的接收请求;（S430）通过改变原始行信息中的存储体信息和行信息的一部分来获取转换行地址;（S450）写或读 通过转换行地址信息对应于数据中原始行信息的数据
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