Abstract:
PURPOSE: A cooperative communication method using a relay node in a cooperative communication network is provided to maximize a channel capacity by selecting a relay node and changing the order of relay nodes in a unidirectional cooperative communication network. CONSTITUTION: A channel capacity between the source node and the destination node is calculated using transmission power about a channel set between a source node and a relay node and transmission power for a channel set between the relay node and a destination node. A relay node for signal transmission is selected by comparing the calculated channel capacities according to each relay node.
Abstract:
PURPOSE: A cooperative communication method for maximizing a channel capacity in a cooperative communication network is provided to maximize a channel capacity in the cooperative communication network which includes one source node, one relay node, and destination nodes. CONSTITUTION: A destination terminal calculates output of the maximum ratio combination using an SNR(Signal to Noise Raito) about a channel set between a source node and a relay node, an SNR of a channel set between the relay node and a destination node, and an SNR about a channel set between the source node and the destination node. The destination terminal calculates a channel capacity using the calculated out of the maximum ratio combination.
Abstract:
PURPOSE: An improved demodulator using a parity bit, in the constant amplitude coded multicode biorthogonal modulation with trans-biorthogonal block extended code are provided to improve performance by simplifying a complexity. CONSTITUTION: Four correlator banks calculate the correlation value between a received signal and a block orthogonal expansion orthogonal trans-orthogonal denotation. Four correlation alignment blocks are arranged according to the correlation value of each correlator bank. Four bit decision blocks determine three bits according to the index and polarity of the orthogonal trans denotation. A combination unit combines the output of the bit decision blocks and the correlation value of the correlation alignment blocks. A parity tester inspects the parity of the combined output bits.
Abstract:
PURPOSE: A verification method simulating a verification unit designed by an HDL is provided to improve a test coverage about a verification unit by preparing a test code in a software type or a software based on open source. CONSTITUTION: A task is described by an HDL(Hardware Description Language) of a hardware level(S411, S412). A test code is generated in reference to code(S417). The test code is described by an SDL(Software Description Language). The test cord is generated as a stimulus file. The stimulus file is described by the hardware level language. A characteristic of the circuit is verified through the stimulus file(S420).
Abstract:
본 발명은 수신 신호의 제곱값을 2 N 으로 근사화하고 N 비트 시프트 연산을 이용하여 나누기 연산을 수행함으로써 디지털 회로의 복잡도를 감소시키고 채널왜곡을 충분히 보상할 수 있는 등화기 및 이를 이용한 채널 추정 방법에 관한 것이다. 본 발명에 따른 수신 신호의 채널 추정 방법은 프리앰블 구간과 데이터 구간을 포함하는 수신 신호의 채널 추정 방법에 있어서, (a) 상기 프리앰블 구간에서 상기 수신 신호의 제곱값을 2 N 으로 근사화하는 단계; 및 (b) 상기 근사화된 수신 신호의 제곱값의 역수를 이용하여 채널 왜곡을 보상하는 등화기를 구현하는 단계를 포함하는 것을 특징으로 한다.
Abstract:
A parallel processing apparatus of a high speed wideband modem signal is provided to simplify wideband modem design and to reduce power consumption by processing fast-transmitted/received data in parallel with a low speed in the wideband modem. In a parallel processing apparatus of a high speed wideband modem signal, a receiver part comprises a serial/parallel conversion part(220) to convert A bit serial data of a digitally-converted base band signal into N number of A bit parallel data to reduce an operation frequency to 1/N, and a first storing part(230) storing N number of A bit parallel data outputted from the serial/parallel conversion part, and more than one demodulation part performing demodulation as to the N number of A bit parallel data. A transmitter part comprises more than one modulation part performing modulation as to the N number of A bit parallel data, and a second storing part storing the N number of A bit parallel modulation data, and a parallel/serial conversion part converting the N number of A bit parallel modulation data into N number of A bit serial modulation data by increasing the operation frequency to N.
Abstract:
본 발명은 다중코드 코드분할 다중접속 시스템의 QAM 변조 방법 및 복조 방법에 관한 것으로서, 송신단은 입력 비트를 부호화한 정진폭 다중부호 이진직교 변조(CACB; constant amplitude multi-code biorthogonal modulation)를 이용하여 전송심볼의 크기가 일정하게 만든 신호를 QAM 부호화하여 전송속도를 높인다. 수신단은 수신 신호로부터 QAM 연판정기 블록을 거쳐 생성된 신호를 CACB 복호화기를 거쳐 데이터를 복조한다. 본 발명에 따르면, 일반적인 다중코드 코드분할 다중접속 시스템에 비해 대역폭 효율을 크게 개선시킬 수 있고, 이에 따라 전송 속도의 향상을 도모할 수 있다. 정진폭 이진 직교 변조, 다중코드 코드분할 다중접속 시스템, QAM 부호화, QAM 연판정기