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公开(公告)号：KR1020160050961A
公开(公告)日：2016-05-11
申请号：KR1020140150208
申请日：2014-10-31
Applicant: 에스케이하이닉스 주식회사 , 포항공과대학교 산학협력단
Abstract: 본발명에따른메모리장치는메모리부와로직제어부를구비한다. 메모리부는복수개의보정그룹들로분할되고각 보정그룹에는다수의워드들을포함하는데이터가저장되는데이터저장부와, 상기보정그룹마다 1개의패리티가설정되며다수의패리티들이저장되는패리티저장부를구비한다. 로직제어부는상기메모리부에저장된데이터를수신하고, 상기데이터에포함된다수의워드들중 더블비트에러를갖는워드를포함하는에러데이터를검출하고, 상기에러데이터에대응하는패리티를상기패리티저장부로부터수신하며, 상기에러데이터와상기패리티에대해논리(logic) 연산을수행하여상기더블비트에러를갖는워드내에서상기더블비트에러의위치를검출하여보정한다.
Abstract translation: 根据本发明的存储器件具有存储单元和逻辑控制单元。 存储单元包括被分成多个校正组的数据存储部分，用于存储在每个校正组中包括多个单词的数据，以及奇偶校验存储部分，用于存储多个奇偶校验，其中一个奇偶校验被设置为 校正组。 逻辑控制单元接收存储在存储单元中的数据，检测包括数据中包含的多个字中具有双位错误的字的错误数据，从奇偶校验存储部分接收与错误数据相对应的奇偶校验，以及 通过执行关于错误数据和奇偶校验的逻辑运算来检测具有双位错误的字中的双位错误的位置，并校正双位错误。
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公开(公告)号：KR1020160008786A
公开(公告)日：2016-01-25
申请号：KR1020140088927
申请日：2014-07-15
Applicant: 에스케이하이닉스 주식회사 , 포항공과대학교 산학협력단
IPC: G11C29/42 , G11C11/4063
CPC classification number: G11C29/42 , G06F11/1008 , G11C11/4063
Abstract: 본발명은메모리데이터의더블비트에러를보정하는장치및 방법에관한것이다. 본발명의에러보정장치는, 복수개의보정그룹들로분할된메모리장치에연결되며, 상기각 보정그룹에저장된다수의워드들을포함하는데이터에서상기다수의워드들중 더블비트에러를갖는워드를포함하는에러데이터를검출하는 ECC 회로; 상기각 보정그룹에저장된데이터의패리티들을저장하는패리티메모리; 및상기에러데이터를수신하고, 상기패리티들중 상기에러데이터에대응하는패리티를수신하며, 상기에러데이터와상기패리티의배타적논리합연산을수행하여상기더블비트에러를갖는워드내에서상기더블비트에러의위치를검출하여상기 ECC 회로로전송하는로직회로를구비하고, 상기 ECC 회로는상기로직회로에서검출한더블비트에러를보정한다.
Abstract translation: 本发明涉及用于校正存储器数据的双位错误的装置和方法。 用于校正本发明的错误的装置包括：ECC电路，连接到被划分为多个校正组的存储器件，用于检测包括多个字中具有双位错误的字的错误数据，该数据包括存储在 每个矫正组; 用于存储存储在每个校正组中的数据的奇偶校验的奇偶校验存储器; 以及逻辑电路，用于接收错误数据，在奇偶校验之间接收对应于错误数据的奇偶校验，通过对错误执行异或运算来检测具有双位错误的字中的双位错误的位置 数据和奇偶校验，并将双位错误的位置发送到ECC电路。 ECC电路校正由逻辑电路检测到的双位错误。
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公开(公告)号：KR101478276B1
公开(公告)日：2014-12-31
申请号：KR1020130072327
申请日：2013-06-24
Applicant: 포항공과대학교 산학협력단
IPC: G06F12/14
Abstract: The present invention provides a data storage apparatus having a security function and a data storage method thereof, which store frequently used data in cells where data preserve time is short in a state where the data is not encrypted to remove encryption/decryption delay time when a user accesses the frequently used data, improving the performance, and to naturally extinguish non-encrypted data when the system is powered off, allowing only encrypted data to remain in cells where data preserve time is long.
Abstract translation: 本发明提供了一种具有安全功能的数据存储装置及其数据存储方法，该数据存储装置在数据未被加密的状态下将频繁使用的数据存储在数据保持时间较短的小区中，以消除加密/解密延迟时间 用户访问频繁使用的数据，提高性能，并且在系统关闭电源时自然熄灭未加密的数据，只允许加密的数据保留在数据保留时间长的单元格中。
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公开(公告)号：KR1020140065805A
公开(公告)日：2014-05-30
申请号：KR1020120132713
申请日：2012-11-22
Applicant: 삼성전자주식회사 , 포항공과대학교 산학협력단
CPC classification number: H04W52/028 , H04W52/0287 , Y02D70/144 , Y02D70/162
Abstract: Provided are a power reduction method of a multi-path receiver including multi-receiver units, which controls power gating or clock gating of the multi-receiver units based on a synchronization state detected from respective multi-receiver units receiving signals, and a multi-path receiver therefor.
Abstract translation: 提供一种多路径接收机的功率降低方法，包括多接收机单元，其基于从各个多接收机单元接收信号检测到的同步状态来控制多接收机单元的功率门控或时钟门控， 路径接收机。
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Patent Agency Ranking
公开(公告)号：KR102025880B1
公开(公告)日：2019-09-26
申请号：KR1020150073540
申请日：2015-05-27
Applicant: 에스케이하이닉스 주식회사 , 포항공과대학교 산학협력단
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公开(公告)号：KR101925409B1
公开(公告)日：2018-12-05
申请号：KR1020120132713
申请日：2012-11-22
Applicant: 삼성전자주식회사 , 포항공과대학교 산학협력단
Abstract: 신호를 수신하는 다중 수신단들 각각으로부터 검출된 동기 상태를 기초로 다중 수신단들의 클럭 게이팅(clock gating) 또는 파워 게이팅(power gating)을 제어하는 다중 수신단들을 포함하는 다중 경로 수신기의 전력 감소 방법 및 그 다중 경로 수신기를 제공할 수 있다.
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公开(公告)号：KR1020140108886A
公开(公告)日：2014-09-15
申请号：KR1020130022732
申请日：2013-03-04
Applicant: 삼성전자주식회사 , 포항공과대학교 산학협력단
CPC classification number: G06F11/1666 , G06F11/1012
Abstract: The present invention relates to a method and an apparatus for controlling low voltage memory in a mobile communication system.The present invention is equipped with a memory space to save ECCS to reduce areas added to the memory, an ECU, and an interleaver. The present invention processs all multi-bit errors which can occur in a memory row in an error correction unit by dispersing errors in the interleaver.
Abstract translation: 本发明涉及一种用于控制移动通信系统中的低电压存储器的方法和装置。本发明装备有一个存储空间，用于保存ECCS以减少添加到存储器的区域，一个ECU和一个交织器。 本发明通过在交织器中分散误差来处理纠错单元中的存储器行中可能发生的所有多位错误。
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公开(公告)号：KR1020130061865A
公开(公告)日：2013-06-12
申请号：KR1020110128141
申请日：2011-12-02
Applicant: 엘지디스플레이 주식회사 , 포항공과대학교 산학협력단
CPC classification number: H04N5/91 , G06T5/40 , G06T7/11 , G06T2207/20112 , H04N2005/91357
Abstract: PURPOSE: A screen change detection device and a method thereof are provided to generate histograms for each division area of a display screen and compare threshold values of the histograms located in division areas corresponding to adjacent frames, thereby determining screen change for an image of each division area based on a comparison result. CONSTITUTION: A scene change area determination unit(104) calculates each threshold value of histograms of an Nth frame provided from a histogram extraction unit(102) and calculates each threshold value of histograms of an N-1th frame from a memory(103). The scene change area determination unit determines scene change for images of each division area based on a comparison result of threshold values of the histograms located in division areas of the frames. [Reference numerals] (101) Brightness extraction unit; (102) Histogram extraction unit; (103) Memory; (104a) Histogram comparison unit; (104b) Scene change detection unit
Abstract translation: 目的：提供一种画面变更检测装置及其方法，以生成显示画面的每个划分区域的直方图，并且比较位于与相邻帧对应的划分区域中的直方图的阈值，从而确定每个划分的图像的画面变化 区域基于比较结果。 构成：场景变化区域确定单元（104）计算从直方图提取单元（102）提供的第N帧的直方图的每个阈值，并从存储器（103）计算第N-1帧的直方图的每个阈值。 场景变化区域确定单元基于位于帧的分割区域中的直方图的阈值的比较结果来确定每个划分区域的图像的场景变化。 （附图标记）（101）亮度提取单元; （102）直方图提取单元; （103）记忆; （104a）直方图比较单元; （104b）场景变化检测单元
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公开(公告)号：KR1020120084186A
公开(公告)日：2012-07-27
申请号：KR1020110005585
申请日：2011-01-19
Applicant: 삼성전자주식회사 , 포항공과대학교 산학협력단
CPC classification number: G06F15/7867 , G06F1/3287 , G06F8/4432 , G06F8/447 , G06F9/30083 , G06F9/30189 , G06F9/3889 , Y02D10/171 , Y02D50/20 , G06F8/47
Abstract: PURPOSE: A power gating based reconfigurable processor, a compile apparatus thereof and a method thereof are provided to selectively supply the power to a single module in each mode, thereby preventing a waste of the power. CONSTITUTION: A processing unit(101) includes an FU(Function Unit), and processes a first type operation based on a first group including the FU in a first mode, and processes a second type operation based on a second group including the FU in a second mode. A power management unit(103) selectively supplies the power to the first group or the second group according to a mode switching signal or a instruction. The processing unit processes a loop operation by using a CGA(Coarse-Grained Array) module defined in the first group in a CGA mode, and processes the rest by using a VLIW(Very Long Instruction Word) module defined in the second group in a VLIW mode.
Abstract translation: 目的：提供一种基于电源门控的可重构处理器，其编译装置及其方法，以在每种模式中选择性地向单个模块供电，从而防止电力浪费。 构成：处理单元（101）包括FU（功能单元），并且在第一模式中处理基于包括FU的第一组的第一类型操作，并且基于包括FU的第二组处理第二类型操作 第二种模式。 功率管理单元（103）根据模式切换信号或指令有选择地将功率提供给第一组或第二组。 处理单元通过使用CGA模式中的第一组中定义的CGA（粗粒子阵列）模块处理循环操作，并且通过使用在第二组中定义的VLIW（超长指令字）模块处理其余部分 VLIW模式。
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