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公开(公告)号：KR1019940002307B1
公开(公告)日：1994-03-21
申请号：KR1019910026068
申请日：1991-12-30
IPC: H05K3/00
CPC classification number: H05K3/225
Abstract: In the card the copper board for a power supply line contains a power separating wire which separates the upper and the lower section by etching the assistant card with a constant space from the left to the right edge. Rectangular wide through-holes are located in a line between the left edge of the card and the connector and between the right edge and the connector, respectively. Power acceptances up to the number of the copper boards can be achieved with short jump wires between the wide through-holes and the connector holes.
Abstract translation: 在卡中，用于电源线的铜板包括通过从左到右边缘以恒定空间蚀刻辅助卡来分离上部和下部的电力分离线。 矩形宽通孔分别位于卡的左边缘和连接器之间以及右边缘和连接器之间的一条线上。 可以通过宽通孔和连接器孔之间的短跳线来实现高达铜板数量的功率接受。
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公开(公告)号：KR1019930015985A
公开(公告)日：1993-07-24
申请号：KR1019910026068
申请日：1991-12-30
IPC: H05K3/00
Abstract: 본 발명은 상기한 바와 같은 전원 인입용 충을 별도로 두고 보조카드의 에지와 커넥터 사이에 전원 인입용 사각(Rectangular) 모양의 광폭 도통홀(wide through hole)을 배치하여 극히 짧은 점프(jump;sold)로 전원 인입이 가능하고, 커넥터의 로(low)수의 1/2배 까지 전원 인입선수를 제공하는데 그 목적을 두고 있다.
본 발명은 상기와 같은 목적을 달성하기 위하여 전원 인입용 층의 구리판을 커넥터의 2개로(low)마다 보조카드 좌측 에지(edge)에서 우측 에지까지 횡으로 잘라서 상하를 서로 분리시키고, 보조카드 좌측 에지와 커넥터사이, 보조카드 우측 에지와 커넥터 사이에 광폭 도통홀을 각각 일열로 배치한다. 광폭 도통홀과 커넥터 홀 사이 극히 짧은 점프(납땜)로 전원 인입용 층의 구리판을 통하여 시험회로기판의 에지 커넥터로 전원이 인입된다.-
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Patent Agency Ranking
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公开(公告)号：KR1019920005107B1
公开(公告)日：1992-06-26
申请号：KR1019890011510
申请日：1989-08-12
Abstract: A parity checking and generating circuit (3) receives a first valid bit (V) and a second valid bit for comparing them with each other to check the parity and generates parity bits. A first interface circuit outputs 16-bit data to a data link unit, and a data selecting circuit (27) selects only active data from the data of the diplexing data link unit. A second interface circuit includes means (21,22) for latching and driving the 16-bit data, and a clock selecting and distributing circuit furnishes synchronizing clocks to the data which are interfaced. With the apparatus, an interfacing is made possible within a time switch.
Abstract translation: 奇偶校验和产生电路（3）接收第一有效位（V）和第二有效位，用于将它们彼此进行比较以检查奇偶校验并产生奇偶校验位。 第一接口电路将16位数据输出到数据链路单元，数据选择电路（27）仅从双工数据链路单元的数据中选择活动数据。 第二接口电路包括用于锁存和驱动16位数据的装置（21,22），以及时钟选择和分配电路，为接口的数据提供同步时钟。 利用该装置，可以在时间切换内进行接口。
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公开(公告)号：KR1019920005064B1
公开(公告)日：1992-06-26
申请号：KR1019890012182
申请日：1989-08-26
Abstract: The unit includes a first multiplexer (1) for receiving differential data signals to output them in the form of parallel data. A transmission data link interfacing unit (3) receives parallel data from a transmission time slot exchange unit (2) to convert them into differential parallel data. A first demultiplexer (4) receives various service signals to output them in the form of differential parallel data, and a second multiplexer (5) receives service signals and the output signals of the first demultiplexer (4) to multiplex them into parallel data. The circuit further includes a second demultiplexer (8), and a testing and maintenance unit (9).
Abstract translation: 该单元包括用于接收差分数据信号以以并行数据的形式输出的第一多路复用器（1）。 传输数据链路接口单元（3）从传输时隙交换单元（2）接收并行数据，将它们转换为差分并行数据。 第一解复用器（4）接收各种服务信号以以差分并行数据的形式输出它们，第二多路复用器（5）接收服务信号和第一多路分解器（4）的输出信号以将它们复用成并行数据。 电路还包括第二解复用器（8）和测试和维护单元（9）。
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公开(公告)号：KR1019920005062B1
公开(公告)日：1992-06-26
申请号：KR1019890011509
申请日：1989-08-12
IPC: H04Q11/04
Abstract: The circuit includes a differential line receiver (1) for receiving differential communication data from a sub-highway to convert them to a single set of communication data. A clock frequency divider (4) receives external clocks to frequency-divide them, and a 1/32 decoder (5) decodes the output of the clock frequency divider (4). A latch section (3) latches the data signals of a means (2) by the clock signals of the clock frequency divider (4), and a parallel data receiver (8) latches externally inputted signal data by the clock signals of the clock frequency divider (4).
Abstract translation: 该电路包括用于从子公路接收差分通信数据以将它们转换为单组通信数据的差分线路接收器（1）。 时钟分频器（4）接收外部时钟以对其进行分频，并且1/32解码器（5）对时钟分频器（4）的输出进行解码。 锁存部分（3）通过时钟分频器（4）的时钟信号锁存装置（2）的数据信号，并行数据接收器（8）通过时钟频率的时钟信号锁存外部输入的信号数据 分隔线（4）。
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