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公开(公告)号：KR1020080050210A
公开(公告)日：2008-06-05
申请号：KR1020070040514
申请日：2007-04-25
Applicant: 한국전자통신연구원
IPC: G01R23/02
CPC classification number: G01R23/09 , G01R1/28 , G01R19/1659 , G01R23/10
Abstract: A frequency sensing apparatus is provided to maintain safety of a hardware device by removing dangerous elements from the hardware device through sensing of changes in the frequency of a clock signal. A frequency sensing apparatus includes an integrator(11) and a comparator(12). The integrator receives clock signals and integrates the received clock signals. The comparator compares an output of the integrator with a predetermined threshold voltage. An output of the comparator indicates whether the clock signal is within a normal frequency range or not. The predetermined threshold voltage is set as a predetermined voltage equal to and more than an output voltage of the integrator corresponding to a lower limit frequency of the normal frequency range of the clock signal.
Abstract translation: 提供了一种频率感测装置，用于通过感测时钟信号频率的变化来从硬件装置中去除危险元件来维持硬件装置的安全性。 频率感测装置包括积分器（11）和比较器（12）。 积分器接收时钟信号并对接收到的时钟信号进行积分。 比较器将积分器的输出与预定阈值电压进行比较。 比较器的输出指示时钟信号是否处于正常频率范围内。 预定阈值电压被设定为等于并且大于与时钟信号的正常频率范围的下限频率相对应的积分器的输出电压的预定电压。
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12.发明授权
公开(公告)号：KR100484487B1
公开(公告)日：2005-04-20
申请号：KR1020020066100
申请日：2002-10-29
Applicant: 한국전자통신연구원
Abstract: 모듈러 연산 장치 및 방법, 그리고 RSA 암호 연산 시스템이 개시된다. 제1데이터 선택기는 외부로부터 입력되는 n비트의 제1데이터로부터 순차적으로 1비트의 데이터인 제1비트값을 추출하여 출력한다. 제1캐리저장 덧셈기는 추출된 제1비트값에 대응하여 외부로부터 입력되는 모듈러값과 n비트의 제2데이터를 제1비트값과 기저장되어 있는 제2비트값에 따라 합산하여 제1합을 출력하고, 합산과정에서 발생하는 캐리를 상위 비트쪽으로 1비트 이동시켜 제1캐리를 출력한다. 제2캐리저장 덧셈기는 제1합, 제1캐리, 및 제1연산값을 합산하여 산출한 합 및 캐리를 각각 하위 비트쪽으로 1비트 이동시킨 제2합 및 제2캐리를 출력한다. 제1 및 제2레지스터는 각각 n비트의 크기를 가지며, 하위 n/2비트에 제2합 및 제2캐리를 저장한다. 제2데이터는 최초의 제1합 연산과정의 수행시에는 외부로부터 입력되는 n비트의 데이터이고 이후의 제1합 연산과정의 수행시에는 제2레지스터에 저장되어 있는 n비트의 데이터이다. 또한, 제2연산값은 제1레지스터에 저장되어 있는 n비트의 데이터이다. 이로써, 시스템 클럭의 상승 모서리와 하강 모서리를 모두 데이터 처리에 사용할 수 있어 낮은 동작 주파수를 갖는 시스템에서 별도의 주파수 증가 장치를 사용하지 않고 효율적으로 RSA 암호 연산을 수행할 수 있다.
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公开(公告)号：KR100480997B1
公开(公告)日：2005-04-07
申请号：KR1020020082218
申请日：2002-12-21
Applicant: 한국전자통신연구원
IPC: G06F7/52
Abstract: 본 발명은 GF(p) 소수 유한체 곱셈 연산과 GF(2^m)의 이진 유한체 곱셈 연산을 모두 수행하는 곱셈 연산 장치에 관한 것이다. 본 발명에 따른 유한체 곱셈 연산 장치는 GF(p) 소수 유한체 타원곡선 암호 시스템과 GF(2^m) 이진 유한체 타원곡선 암호 시스템을 모두 수용할 수 있고, 같은 비트 길이를 가지는 다양한 타원곡선 암호 시스템을 수용할 수 있어, 시스템 효율을 높일 수 있으며, RSA 암호 시스템의 연산 장치로의 확장이 용이하다.
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公开(公告)号：KR1020040053833A
公开(公告)日：2004-06-25
申请号：KR1020020080285
申请日：2002-12-16
Applicant: 한국전자통신연구원
IPC: H04L9/00
CPC classification number: H04L9/3066
Abstract: PURPOSE: A high-performance encryption device using an elliptic curve is provided to process rapidly a scalar multiplication calculation process by optimizing an elliptic curve calculation method and a window calculation method on a projective coordinate system. CONSTITUTION: A first storage(100) stores multiplication constant k and outputs it at scalar multiplication calculation using a comb method and a multiplication constant of scalar multiplication calculation using a window method. A second storage(300,400) stores input coordinates of an elliptic curve, a result of intermediate calculation, and a result of final calculation. A third storage(500) converts affine coordinates to projective coordinates and the result of intermediate calculation. A fourth storage(600,700) stores new coordinates to perform an addition calculation process of the elliptic curve. A multiplication calculation unit(2000,2100,2200,2300) performs a multiplication calculation process of finite field. A reciprocal calculation unit(2400) performs a reciprocal calculation process of the finite field. An additional calculation unit(1300) calculates various elliptic curves by using the multiplication calculation and the reciprocal calculation unit. A multiplexer unit(800-1000,1500-1900) selects an input of the storage and the inputs of the multiplication calculation and the reciprocal calculation unit. A control unit(1100) performs all operations of each element.
Abstract translation: 目的：提供一种使用椭圆曲线的高性能加密装置，通过在投影坐标系上优化椭圆曲线计算方法和窗口计算方法，快速处理标量乘法运算过程。 构成：第一存储器（100）存储倍数常数k，并使用梳状方法和使用窗口方法的标量乘法运算的乘法常数在标量乘法运算中输出。 第二存储器（300,400）存储椭圆曲线的输入坐标，中间计算的结果和最终计算的结果。 第三个存储（500）将仿射坐标转换为投影坐标，并将中间计算结果转换为投影坐标。 第四存储器（600,700）存储新坐标以执行椭圆曲线的加法运算处理。 乘法运算单元（2000,2100,2200,2300）进行有限域的乘法运算处理。 倒数计算单元（2400）执行有限域的倒数计算处理。 附加计算单元（1300）通过使用乘法运算和倒数计算单元计算各种椭圆曲线。 复用器单元（800-1000,1500-1900）选择存储器的输入和乘法运算的输入以及倒数计算单元。 控制单元（1100）执行每个元件的所有操作。
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公开(公告)号：KR1020040052304A
公开(公告)日：2004-06-23
申请号：KR1020020080156
申请日：2002-12-16
Applicant: 한국전자통신연구원
IPC: G06F1/00
Abstract: PURPOSE: A device and a method for the security of a digital hardware system are provided to encrypt/decrypt data fast by using an exclusive binary operator and a similar random number generator, offer the high security by using an asymmetric encryption algorithm, and reinforce the security of the digital hardware system such as a set-top box or a digital game machine. CONSTITUTION: A hardware block(110) having a hardware security mechanism is equipped with a security target block(100) that is the security target of a CPU or a PCI(Peripheral Component Interconnect) bridge, and a hardware security block(120) providing the hardware security mechanism and performing bidirectional communication while providing the stability for data and an instruction through a hardware system bus(130). The hardware security block includes a key distribution controller(140), a controller(150), the similar random number generator(160), the exclusive binary operator(170), and the asymmetric encryption module(180).
Abstract translation: 目的：提供一种用于数字硬件系统安全的设备和方法，通过使用独有的二进制运算符和类似的随机数生成器快速加密/解密数据，通过使用非对称加密算法提供高安全性，并加强 诸如机顶盒或数字游戏机的数字硬件系统的安全性。 构成：具有硬件安全机制的硬件块（110）配备有作为CPU或PCI（外围组件互连）桥的安全目标的安全目标块（100）和提供 硬件安全机制并执行双向通信，同时通过硬件系统总线提供数据的稳定性和指令（130）。 硬件安全块包括密钥分配控制器（140），控制器（150），类似的随机数生成器（160），专用二进制运算符（170）和非对称加密模块（180）。
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Patent Agency Ranking
公开(公告)号：KR1020040037555A
公开(公告)日：2004-05-07
申请号：KR1020020066100
申请日：2002-10-29
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A device and a method for operating modular, and an RAS(Rivest-Shamir-Adleman) operating system for the same are provided to improve efficiency of a modular operation for the RSA encryption operation of the system having a low-operation frequency. CONSTITUTION: The RSA operator(110) comprises data selection parts(200, 210), a modular operator(220), and a path selection part(230). The data selection parts(200, 210) select a data between a data from an input interface(100), and a data received from the path selection part(230). The modular operator(220) comprises a modular multiplier(220-1) and a reduction part(220-2). The modular multiplier(220-1) performs a Montgomery operation. The reduction part(220-2) performs third step of a formula 3. The path selection part(230) provides result value of each modular operations to the data selection parts(200, 210) while the modular operation is executed. The path selection part(230) outputs result value when the modular operation is terminated.
Abstract translation: 目的：提供一种用于操作模块化的设备和方法，以及用于其的RAS（Rivest-Shamir-Adleman）操作系统，以提高具有低操作频率的系统的RSA加密操作的模块化操作的效率。 构成：RSA操作器（110）包括数据选择部件（200,210），模块化操作器（220）和路径选择部件（230）。 数据选择部分（200,210）选择来自输入接口（100）的数据和从路径选择部分（230）接收的数据之间的数据。 模块化操作器（220）包括模数乘法器（220-1）和减速部分（220-2）。 模块化乘法器（220-1）执行蒙哥马利运算。 还原部分（220-2）执行公式3的第三步骤。当执行模块化操作时，路径选择部分（230）向数据选择部分（200,210）提供每个模块化操作的结果值。 当模块化操作终止时，路径选择部分（230）输出结果值。
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公开(公告)号：KR100419485B1
公开(公告)日：2004-02-19
申请号：KR1020010044113
申请日：2001-07-23
Applicant: 한국전자통신연구원
IPC: G06K19/07
Abstract: PURPOSE: A power supply unit for an IC card and a method for controlling the same are provided to minimize an electric power consumption necessary for driving a system and perform a stable operation in an IC card system having an internal power source(battery). CONSTITUTION: An internal power source(110) supplies a power source of a predetermined level in the case that an internal circuit unit(200) of a card system is an operation mode or a waiting mode. A switching control circuit unit(120) receives a mode judgement signal from a mode judgement unit in the internal circuit unit(200) which judges whether the card system is an operation mode or a waiting mode, and supplies a switching control signal to the first switching unit(140) and the second switching unit(141) in accordance with the received mode judgement signal, respectively. That is, in the case that the card system is an operation mode, the switching control circuit unit(120) supplies a switching control signal to the first switching unit(140) for making the internal power source(110) be supplied to the internal circuit unit(200) and making the internal power source(110) be accumulated in an electric charge accumulating circuit unit(130). Also, the switching control circuit unit(120) supplies a switching control signal to the second switching unit(141) for making an electric charge be accumulated in an electric charge accumulating circuit unit(130).
Abstract translation: 目的：提供一种用于IC卡的供电单元及其控制方法，以使驱动系统所需的电力消耗最小化，并在具有内部电源（电池）的IC卡系统中执行稳定的操作。 构成：在卡系统的内部电路单元（200）是工作模式或等待模式的情况下，内部电源（110）提供预定电平的电源。 开关控制电路单元（120）从判定卡系统是工作模式还是等待模式的内部电路单元（200）中的模式判断单元接收模式判断信号，并将切换控制信号提供给第一 切换单元（140）和第二切换单元（141）分别根据接收到的模式判断信号进行切换。 也就是说，在卡系统是操作模式的情况下，切换控制电路单元（120）向第一切换单元（140）提供切换控制信号，以使内部电源（110）被提供给内部 （200），并使内部电源（110）蓄积在电荷蓄积电路部（130）中。 此外，切换控制电路单元（120）将切换控制信号提供给第二切换单元（141），以使电荷积聚在电荷积聚电路单元（130）中。
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公开(公告)号：KR100406138B1
公开(公告)日：2003-11-14
申请号：KR1020010074631
申请日：2001-11-28
Applicant: 한국전자통신연구원
IPC: H04L9/14
Abstract: PURPOSE: An NTRU encoding/decoding device is provided to perform efficiently an NTRU encoding/decoding process by improving a structure of the NTRU encoding/decoding device. CONSTITUTION: The first storage portion(12) stores an input message for NTRU encoding and a secret key for NTRU decoding. The second storage portion(13) stores an input value of a polynomial expression using p as a modular value of a coefficient. The third storage portion(14) stores an input value of a polynomial expression using q as a modular value of a coefficient. An NTRU calculation portion(16) performs an NTRU cryptographic calculation and a decoding calculation for values of the first to the third storage portions. The fourth storage portion(17) stores an output value of the NTRU calculation portion. An output selection portion(18) determines an output operation of the fourth storage portion. A modular calculation portion(19) performs a modular calculation process for an output value of the output selection portion. An NTRU control portion(15) controls each register and the NTRU calculation portion.
Abstract translation: 目的：提供一种NTRU编码/解码设备，通过改进NTRU编码/解码设备的结构来有效地执行NTRU编码/解码处理。 构成：第一存储部分（12）存储用于NTRU编码的输入消息和用于NTRU解码的秘密密钥。 第二存储部分（13）存储使用p作为系数的模值的多项式的输入值。 第三存储部分（14）存储使用q作为系数的模值的多项式的输入值。 NTRU计算部分（16）对第一至第三存储部分的值执行NTRU密码计算和解码计算。 第四存储部分（17）存储NTRU计算部分的输出值。 输出选择部分（18）确定第四存储部分的输出操作。 模块计算部分（19）对输出选择部分的输出值执行模块计算处理。 NTRU控制部分（15）控制每个寄存器和NTRU计算部分。
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公开(公告)号：KR1020030048243A
公开(公告)日：2003-06-19
申请号：KR1020010078127
申请日：2001-12-11
Applicant: 한국전자통신연구원
IPC: G06F7/44
Abstract: PURPOSE: A device for a modular multiplication is provided to execute a modular multiplication at high speed by repeating a bit multiplication and executing a modular multiplication of data more than a specific bit, thereby reducing a circuit area of a modular multiplication device, and a reducing memory accessing times using a register for storing a mid-point. CONSTITUTION: A memory(160) stores data for executing a modular multiplication of information. A processor requests the modular multiplication and loads/uses the multiplication results from the memory(160). A register(230) receives data for a modular multiplication from the memory(160), stores the data, and stores a mid-point being generated during the modular multiplication. A modular circuit(240) repeats a bit multiplication calculation, executes a modular multiplication of data which are greater than a specific bit, and stores a mid-point in the register(230) and a result value in the memory(160). A reduction circuit(250) corrects the result value selectively in accordance with a comparison result of the result value and the modular value. A control circuit(220) outputs various kinds of control signals to the register(230), the modular circuit(240), and the reduction circuit(250), and controls the modular multiplication.
Abstract translation: 目的：提供一种用于模乘的装置，通过重复比特乘法和执行比特定比特数据的模数乘法，高速执行模乘法，从而减少了乘法装置的电路面积，并减少了 使用寄存器存储中点的存储器存取时间。 构成：存储器（160）存储用于执行信息的模数乘法的数据。 处理器请求模乘，并加载/使用来自存储器的乘法结果（160）。 寄存器（230）从存储器（160）接收用于模数乘法的数据，存储数据，并存储在模乘期间生成的中点。 模块化电路（240）重复位乘法计算，执行大于特定位的数据的模乘，并将寄存器（230）中的中点和结果值存储在存储器（160）中。 还原电路（250）根据结果值和模块值的比较结果有选择地校正结果值。 控制电路（220）向寄存器（230），模块电路（240）和还原电路（250）输出各种控制信号，并控制模乘。
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公开(公告)号：KR1020020095937A
公开(公告)日：2002-12-28
申请号：KR1020010034306
申请日：2001-06-18
Applicant: 한국전자통신연구원
IPC: G09C1/00
Abstract: PURPOSE: An ellipse curve encryption device is provided to have a high security with maintaining a short key so as to authenticate a user in a system restricted in area such as an integrated(IC) card and to exchange the key values of the symmetric key system. CONSTITUTION: An ellipse curve encryption device includes a first storing register(201) for storing operational coefficient values of an ellipse curve encryption, a second storing register(202) for storing input values of operation for the ellipse curve encryption, an ellipse curve encryption operation module(205) for implementing the ellipse curve encryption operation by using the valued stored at the first and the second registers(201,202), a third register(203) for inputting to the ellipse curve encryption operation module(205) so as to use the following operation after the output value form the ellipse curve encryption operation module is stored at the register and an ellipse curve encryption controller(204) for controlling the ellipse curve encryption operation module(205) in response to the value stored the first register(201) and for managing the transmission of the operation result.
Abstract translation: 目的：提供一种椭圆曲线加密装置，具有保持短密钥的高安全性，以便对诸如集成（IC）卡等区域限制的系统中的用户进行认证，并交换对称密钥系统的密钥值 。 构成：椭圆曲线加密装置包括用于存储椭圆曲线加密的运算系数值的第一存储寄存器（201），用于存储用于椭圆曲线加密的输入值的第二存储寄存器（202），椭圆曲线加密运算 模块（205），用于通过使用在第一和第二寄存器（201,202）处存储的值来实现椭圆曲线加密操作;第三寄存器（203），用于输入到椭圆曲线加密操作模块（205），以便使用 在输出值形成椭圆曲线加密操作模块之后的以下操作被存储在寄存器和用于响应于存储第一寄存器（201）的值的控制椭圆曲线加密操作模块（205）的椭圆曲线加密控制器（204） 并且用于管理操作结果的传输。
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