Abstract:
1. 청구범위에 기재된 발명이 속한 기술분야 본 발명은 라우터 프로세서의 제어 경로 구성을 위한 스위칭 장치 및 그 방법에 관한 것임. 2. 발명이 해결하려고 하는 기술적 과제 본 발명은 라우터 시스템에서 프로세서 간에 복수의 제어 경로(Control Path)를 구성하고, 프로세서가 하나의 이더넷 채널과 주소로 다른 프로세서와 통신 가능하게 하며, 제어 경로(Control Path) 상의 루프 현상을 자동 제거하게 함으로써, 프로세서의 부하를 낮추고, 제어 경로(Control Path) 구성과 고장 대응 방법을 단순화시켜 라우터 시스템의 신뢰성과 가용성을 높이고, 시스템 확장에 있어 설계와 구현의 용이성을 높일 수 있는 라우터 프로세서의 제어 경로 구성을 위한 스위칭 장치 및 그 방법을 제공하는데 그 목적이 있음. 3. 발명의 해결방법의 요지 본 발명은, 엘2(L2) 메인보드 상에 장착되고, 라우터 프로세서의 제어 경로 구성을 위한 스위칭 장치에 있어서, 상기 엘2(L2) 메인보드의 전원을 감시하기 위한 전원감시수단; 상기 엘2(L2) 메인보드를 관리하기 위한 프로세싱 수단; 상기 엘2(L2) 메인보드를 적어도 하나 이상 연결하기 위한 에지 엘2(L2) 스위치와 상기 에지 엘2(L2) 스위치를 연결하기 위한 코어 엘2(L2) 스위치를 포함하는 엘2(L2) 스위칭 수단; 및 상기 전원감시수단의 출력 신호와, 상기 프로세싱 수단의 출력 신호와, 상대 엘2(L2) 메인보드의 작동 상태 입력과, 상기 엘2(L2) 메인보드의 슬롯 식별자와, 상기 엘2(L2) 스위칭 수단에 연결된 이더넷의 링크 상태를 입력받아 그 정보를 보관하고, 자신의 동작 상태를 알리기 위한 엘2(L2) 스위치 제어수단을 포함함. 4. 발명의 중요한 용도 본 발명은 통신 시스템 등에 이용됨. 라우터, 제어 경로(Control Path), 이더넷, 코어 스위치, 에지 스위치, 제어 로직
Abstract:
PURPOSE: A method and apparatus for switching packet/TDM including a TDM circuit and a carrier Ethernet packet signal are provided to switch a TDM circuit signal and a carrier Ethernet signal and to transfer a packet without restriction. CONSTITUTION: A packet/TDM(Time Division Multiplexing) selection unit(310) classifies an Ethernet packet signal, which is received from an Ethernet matching unit(100), into a TDM signal. A packet switch(330) switches a signal in which the conversion of a TDM signal path is required. A TDM switch(350) switches the signal in which the conversion of the Ethernet packet signal path is required. A converter(370) performs the conversion of the Ethernet packet signal.
Abstract:
PURPOSE: A node device and method for receiving an optical signal of the same, and a ring network system thereof are provided to composes a ring network system at a low cost. CONSTITUTION: A source node device among node devices(100a) transmits an optical signal through a transmission medium by using a wavelength division multiplexing. A transmission device(102a) outputs at least one optical wave signal, which is desired to be transmitted, to multiplexing device(104). A multiplexing device generates an optical signal by multiplexing the outputted wavelength signal forma transmission device and outputs an optical signal to an optical combination unit(106). An optical combining unit combines an optical signal which itself will transmit and the optical signal transmitted from another node device. An amplifier device(108) transmits a next node device(100b) through an optical fiber by amplifying the optical signal combined in the optical combining unit.
Abstract:
A single router system through dual tree-type control paths among plural router boxes is provided to bind various router boxes to expand the bound boxes into one single router system and to simplify a control path configuration in accordance with the expansion and a malfunction coping method, thereby increasing availability and reliability of the router system. Power is applied(600), and IDs of boxes are read as an internal processor starts operating(601). It is decided whether to boot to sub boxes or to continue a standby box booting process, depending on whether the IDs of the boxes are IDs of the sub boxes(602,603). If not the IDs of the sub boxes, it is decided whether the IDs are IDs of active boxes(604). If not, an OS(Operating System) suited to standby boxes is booted, and a system state is checked(606). It is decided whether active boxes exist within a system(607). According to the decided results, the active boxes are booted(608) or the standby boxes are initialized while driving applications(609).
Abstract:
A QoS-guaranteed switched router system is provided to construct a QoS-guaranteed network without having to change an existing Internet access network in constructing a broadband convergence network by providing flow-based packet classification and intelligent congestion control. The first and second line processing units(11,12) perform flow-based processing on an Internet protocol or multi-protocol label switch packet selectively received through a line interface of an n-gigabit Ethernet having the m number of ports or an m-gigabit Ethernet having the n number of ports according to each application. An application processing unit(13) downloads a booting process and software load data of the first and second line processing units(11,12), manages a system including alarm, log, statistics and performance monitoring by collecting management information from the first and second line processing units, and provides an external interface that is able to manage the system.
Abstract:
A memory system of a flexible serial interface mode and a memory access method thereof are provided to reduce time/expense required for designing the system, and facilitate design/implementation for extending a memory capacity by configuring memory connection in a memory controller based on a flexible serial link and virtual setting/changing an address of the memory. The memory system includes at least one memory(9) and a memory controller(1). The memory controller flexibly sets serial link connection irrespective of physical position/order of serial ports(3) and transceives memory data through the serial link connection by using a serial port. The memory controller changes the number of available serial links(4) connecting to the memory according to circumstances. The memory controller includes an address decoder, a memory data transmitter detecting/transmitting a memory ID corresponding to the memory address, processing the data, and initializing/managing the memory, a memory data converter, and a plurality of serial ports transmitting the memory data to the memory through the serial link in a fast serial mode.
Abstract:
PURPOSE: An inter-processor communication system and a method for the same are provided to solve problems like a restriction of the number of signal lines, an additional cost caused by a usage of a commercial communication chip, and a load of a software for operating a communication between processors. CONSTITUTION: The system comprises a processor card data communication controller(31) and a line card data communication controller(32). The processor card data communication controller(31) accesses each line card by a polling method, checks a possibility of communicating data, and plays a role of a master data communication. The line card data communication controller(32) receives a polling signal from the processor card data communication controller(31), and communicates data based on a slave scheme.
Abstract:
PURPOSE: An inter-processor communication system and a method for the same are provided to solve problems like a restriction of the number of signal lines, an additional cost caused by a usage of a commercial communication chip, and a load of a software for operating a communication between processors. CONSTITUTION: The system comprises a processor card data communication controller(31) and a line card data communication controller(32). The processor card data communication controller(31) accesses each line card by a polling method, checks a possibility of communicating data, and plays a role of a master data communication. The line card data communication controller(32) receives a polling signal from the processor card data communication controller(31), and communicates data based on a slave scheme.