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公开(公告)号：KR1019970002734B1
公开(公告)日：1997-03-08
申请号：KR1019930025038
申请日：1993-11-23
Applicant: 한국전자통신연구원
IPC: H04L23/02
Abstract: A soft-quantization hadamard demodulator is disclosed. The soft-quantization hadamard demodulator demodulates a hadamard orthogonal modulation signal soft-quantized in a reverse link receiving stage of a CDMA spread spectrum system. The soft-quantization hadamard demodulator may improve approximately 2dB, as compared with a hard-quantization scheme, by demodulating the hadamard modulation signal soft-quantized. Also, the soft-quantization hadamard demodulator may improve the performance of a mobile communication system in serious noise environment.
Abstract translation: 公开了一种软量化的哈萨姆解调器。 软质量化哈马达解调器解调在CDMA扩频系统的反向链路接收级中软量化的哈达玛正交调制信号。 与硬量化方案相比，软质量化哈塔马斯解调器可以通过对软质量化的哈达调制信号进行解调来提高约2dB。 此外，软质量化的哈马达解调器可以在严重的噪声环境中提高移动通信系统的性能。
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公开(公告)号：KR1019960003101B1
公开(公告)日：1996-03-04
申请号：KR1019930025730
申请日：1993-11-29
Applicant: 한국전자통신연구원
IPC: H04B7/216
Abstract: The Walsh-Hadamard function index generator includes the steps of: exclusive logical adding the outputs after logical multiplying of the outputs of row and column index calculators; and multiplying the final output of M dimension calculator and N/M dimension calculator or N/M dimension calculator or M dimension calculator.
Abstract translation: Walsh-Hadamard函数索引生成器包括以下步骤：在逻辑乘法后，排列逻辑地将行和列索引计算器的输出相乘; 并乘以M维度计算器和N / M维度计算器或N / M维度计算器或M维度计算器的最终输出。
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公开(公告)号：KR1019950016051A
公开(公告)日：1995-06-17
申请号：KR1019930025730
申请日：1993-11-29
Applicant: 한국전자통신연구원
IPC: H04B7/216
Abstract: 본 발명은 확산대역 이동통신 시스템 등에서 신호간의 간섭 효과를 제거할 목적으로 사용되는 왈시-하다마드(Walsh-Hacdamard) 함수열 생성기에 관한 것으로, 가로열 계수기와 세로열 계수기 출력을 논리곱한 후 그 출력들이 배타적 논리수합수단을 거치게함으로써 최종 출력의 함수열이 왈시-하다마드 함수열이 되게 하는 N차원 왈시-하다마드 함수열 생성기에 있어서, 상기 계수기는 N/M차계수기; M차 계수기; 및 상기 N/M차 계수기측과 M차 계수기측의 최종 출력을 다중화하는 다중화수단을 구비하여 이루어짐으로써 순방향 링크 및 역방향 링크에 사용되는 왈시-하다마드 함수열을 고속으로 생성하는 효과가 있다.
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Patent Agency Ranking
公开(公告)号：KR1019910009808B1
公开(公告)日：1991-11-30
申请号：KR1019890008113
申请日：1989-06-13
Inventor： 신동관
IPC: H03K7/06
CPC classification number: H03L7/0814 , H03L7/0812 , H04L7/0008 , H04L7/0337
Abstract: a phase detecting and re-timing block (U1) comprising two OR gates, two D flip-flops, two XOR gates and two line connection OR means appling the status signal to the loop processor by detecting the difference of the input clock and the input data; a loop processor (U2) generating the control signal to get the correct value of the phase difference between the input clock and data; and a phase mover (U3) outputting the input data which phase is controlled by the OR gate according to the control signal of the loop processor.
Abstract translation: 包括两个或门，两个D触发器，两个XOR门和两个线路连接OR装置的相位检测和重新定时块（U1），通过检测输入时钟和输入的差异将状态信号施加到环路处理器 数据; 产生控制信号以获得输入时钟和数据之间的相位差的正确值的循环处理器（U2）; 以及根据循环处理器的控制信号输出由或门控制相位的输入数据的相位移动器（U3）。
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公开(公告)号：KR1019900004301B1
公开(公告)日：1990-06-20
申请号：KR1019860011546
申请日：1986-12-30
Applicant: 한국전자통신연구원
IPC: H04L25/493 , H04L25/40
Abstract: The circuit for reducing output Jitter by eliminating phase difference of alpha (II) includes a first exlusive OR gate (Ex-OR1) for adding input signal through delay circuit (U3) and input pulse for making rectangular wave dependent to position of timing clock, a second exclusive OR gate (Ex-OR2) for modulating two input pulse (S3,S10) into rectangular wave with half wave pulse width, and a loop filter (U4) for eliminating phase difference of alpha (II) between output pulses of the first and the third exclusive OR gate.
Abstract translation: 通过消除α（II）的相位差来减小输出抖动的电路包括用于通过延迟电路（U3）添加输入信号的第一个异或或门（Ex-OR1）和用于使矩形波取决于定时时钟的位置的输入脉冲， 用于将两个输入脉冲（S3，S10）调制成具有半波脉冲宽度的矩形波的第二异或门（Ex-OR2）和用于消除半波脉冲的输出脉冲之间的α（II）的相位差的环路滤波器（U4） 第一和第三异或门。
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