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公开(公告)号：KR1019970007277B1
公开(公告)日：1997-05-07
申请号：KR1019940015283
申请日：1994-06-29
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: The present invention relates to apparatus and method for making a communication between multiple processors having the relationship of master and slave. If a master processor stores a command being pre-defined according to a kind of works to be processed by a slave processor into a shared memory, the slave processor performs a work according to a stored content of the shared memory. The apparatus includes: a control processor for processing a control signal between a master processor and a slave processor; a shared memory for storing a command and information according to a control signal of the slave processor, and storing a work result of the slave processor; an address buffer for controlling an address direction of the shared memory, and managing an area of the address buffer of the shared memory; a data buffer for controlling a data direction of the shared memory, and managing an area of a data bus of the shared memory; a master processor which applies an interrupt signal to the slave processor when there is a work to be processed by the slave processor, and uses a work process result stored in the shared memory when the interrupt signal is applied from the slave processor; and a slave processor which transmits a shared memory use response signal to the master processor when a shared memory use request signal is received from the master processor, processes a corresponding work according to a command and information stored in the shared memory when receiving an interrupt signal from the control processor, stores a working result into the shared memory, and changes an address space of the shared memory to its own address space when receiving a control signal of the shared memory after applying an interrupt signal to the master processor.
Abstract translation: 本发明涉及具有主从关系的多个处理器之间进行通信的装置和方法。 如果主处理器根据要由从属处理器处理的作品的种类将预定义的命令存储到共享存储器中，则从属处理器根据存储的共享存储器的内容执行工作。 该装置包括：用于处理主处理器和从处理器之间的控制信号的控制处理器; 共享存储器，用于根据从属处理器的控制信号存储命令和信息，并存储从属处理器的工作结果; 用于控制共享存储器的地址方向的地址缓冲器，以及管理共享存储器的地址缓冲器的区域; 用于控制共享存储器的数据方向的数据缓冲器，以及管理共享存储器的数据总线的区域; 主处理器，当存在由从处理器处理的工作时，将中断信号施加到从属处理器，并且当从从属处理器施加中断信号时，使用存储在共享存储器中的工作处理结果; 以及当从主处理器接收到共享存储器使用请求信号时，向主处理器发送共享存储器使用响应信号的从属处理器，当接收到中断信号时，根据存储在共享存储器中的命令和信息处理对应的工作 从控制处理器将工作结果存储到共享存储器中，并且在向主处理器应用中断信号之后接收到共享存储器的控制信号时，将共享存储器的地址空间改变为其自己的地址空间。
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公开(公告)号：KR1019960002031A
公开(公告)日：1996-01-26
申请号：KR1019940015283
申请日：1994-06-29
Applicant: 한국전자통신연구원
IPC: G06F13/38
Abstract: 본 발명은 주종관계를 갖는 다중프로세서간의 통신장치에 관한 것으로, 특히 주로프로세서(11)와 종프로세서(21)를 갖는 다중프로세서 시스템에 있어서, 종프로세서(21)를 제어하기 위한 상기 주프로세서(11)의 제어신호를 처리하는 제어처리부 (30)와, 상기 주 프로세서(11)와 종프로세서(21)간의 통신을 위한 메일박스 형태의 공유메모리(60)의 어드레스 방향을 제어하고 공유메모리의 어드레스 버승의 소유영역을 관리하는 어드레스버퍼(40)와, 상기 공유메모리(60)의 데이타버퍼(50)로 이루어져 시스템에서 정의된 명령어를 사용할 수 있게 함으로써 종프로세서가 처리해야할 작업의 종류가 많은 시스템에 다양하게 적용가능하고, 멀티타스킹 처리를 요하는 분야에도 적용 가능하며, 주ㆍ종 프로세서가 서로 독립적으로 동시에 작업을 처리함으로써 시스템의 효율 및 성능을 증가시킬 수 있다.
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