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公开(公告)号：KR101326117B1
公开(公告)日：2013-11-06
申请号：KR1020130072977
申请日：2013-06-25
Applicant: 홍익대학교 산학협력단
IPC: H03L7/081
CPC classification number: H03L7/0814
Abstract: The present invention relates to a digital delay-locked loop circuit using a phase-inversion lock algorithm and a method for controlling the same. The digital delay-locked loop circuit comprises: a phase-inversion lock control circuit which controls whether to use the phase-inversion lock algorithm by detecting a phase difference between an input clock and an output clock; an inverter which outputs an inverted input clock after inverting the input clock; a multiplexer which receives the input clock and the inverted input clock output from the inverter as an input signal, and outputs the input clock or the inverted input clock according to a control signal of the phase-inversion lock control circuit; and a phase-synchronization unit which is connected to an output terminal of the multiplexer, and performs phase-synchronization after receiving an output signal of the multiplexer. [Reference numerals] (110) Reversal locking control circuit;(140) Three step digital control delay line (TDCDL);(141) 1'st DCDL (delay resolution = �t1);(142) 2'st DCDL (delay resolution = �t2 = �t1/2);(143) FDL (delay resolution = �t3 = �t2/16);(150) Phase detector;(160) 9-bit variable successive approximate register;(170) 4-to-16 thermometer decoder;(180) Successive approximate register control circuit
Abstract translation: 本发明涉及使用相位反转锁定算法的数字延迟锁定环路电路及其控制方法。 数字延迟锁定环电路包括：相位反转锁定控制电路，通过检测输入时钟和输出时钟之间的相位差来控制是否使用相位反转锁定算法; 反相器，其在反相输入时钟之后输出反相输入时钟; 接收从反相器输出的输入时钟和反相输入时钟作为输入信号的多路复用器，并根据相位反转锁定控制电路的控制信号输出输入时钟或反相输入时钟; 以及相位同步单元，其连接到所述多路复用器的输出端，并且在接收到所述多路复用器的输出信号之后执行相位同步。 （110）反转锁定控制电路;（140）三步数字控制延迟线（TDCDL）;（141）第一DCDL（延迟分辨率= t1）;（142）第二DCDL（延迟分辨率 = t2= t1/ 2）;（143）FDL（延迟分辨率= t3= t2/ 16）;（150）相位检测器;（160）9位可变连续近似寄存器;（170） -16温度计解码器;（180）连续近似寄存器控制电路
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12.发明公开
公开(公告)号：KR1020120054319A
公开(公告)日：2012-05-30
申请号：KR1020100115640
申请日：2010-11-19
Applicant: 홍익대학교 산학협력단
CPC classification number: H03L7/0814 , G06F1/04 , H04L7/0338
Abstract: PURPOSE: An apparatus for generating diffused spectrum clock signals with a phase interpolator and a method using the same are provided to diffuse the spectrum of clock signals without the distortion of a clock duty cycle rate by easily modulating a triangular frequency through a phase interpolate technology. CONSTITUTION: An apparatus for generating diffused spectrum clock signals includes a delay locked loop circuit unit(100) and a diffused spectrum generating unit(200). The delay locked loop circuit unit is composed of a voltage control delay line, a phase detector, and a charge pump. The delay locked loop circuit unit provides a reference clock signal having a frequency of 200MHz to the diffused spectrum generating unit. The diffused spectrum generating unit diffuses spectrums by performing the triangular frequency modulation of the reference clock signal provided from the delay locked loop circuit unit.
Abstract translation: 目的：提供一种使用相位内插器产生扩散频谱时钟信号的装置及其使用方法，通过相位内插技术容易地调制三角频率来扩展时钟信号频谱，而不会造成时钟占空比失真。 构成：用于产生扩散频谱时钟信号的装置包括延迟锁定环电路单元（100）和扩散频谱产生单元（200）。 延迟锁定环电路单元由电压控制延迟线，相位检测器和电荷泵组成。 延迟锁定环电路单元向扩散频谱发生单元提供具有200MHz频率的参考时钟信号。 扩散频谱发生单元通过对从延迟锁定环电路单元提供的参考时钟信号进行三角频率调制来扩频。
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Patent Agency Ranking
公开(公告)号：KR101601113B1
公开(公告)日：2016-03-08
申请号：KR1020140111193
申请日：2014-08-26
Applicant: 홍익대학교 산학협력단
IPC: H01P1/36
Abstract: 본발명은비가역회로소자를개시한다. 상기비가역회로소자는공진기와상기공진기가결합되고회로소자가실장되는유전체기판을포함하며, 직류자계인가시상기회로소자의값에대응되는주파수대역에서각각독립적으로구동하는복수개의자성조립체; 상기복수개의자성조립체의양단에서상기직류자계를인가하기위한제1, 제2 영구자석; 및상기복수개의자성조립체와전기적으로연결되고, 상기복수개의자성조립체와상기제1, 제2 영구자석을물리적으로고정하며, 시스템으로부터입력되는신호를상기주파수대역에서구동하는상기복수개의자성조립체를거쳐서출력시키는표면실장용유전체기판;을포함한다.
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公开(公告)号：KR101478037B1
公开(公告)日：2015-01-02
申请号：KR1020140044144
申请日：2014-04-14
Applicant: 홍익대학교 산학협력단
CPC classification number: H04L25/06
Abstract: 저스윙 저전력 니어-그라운드 시그널링 송수신기 및 그 동작 방법이 개시된다.
저스윙 저전력 니어-그라운드 시그널링 송수신기의 송신 장치는 제어 신호에 따라 제어된 공급 전압을 출력하는 전원 공급 블록; 및 전단 구동기가 출력한 입력 신호에 따라 데이터 신호를 생성하며, 공급 전압에 따라 데이터 신호의 진폭을 제어하는 출력단을 포함할 수 있다.Abstract translation: 本发明涉及一种低摆幅低功率近地信号收发信机及其操作方法。 低摆幅低功率近地信号收发器的发射机包括：电源模块，用于输出根据控制信号控制的电源电压; 以及输出端子，其根据从前一级驱动器输出的输入信号生成数据信号，以根据电源电压来控制数据信号的幅度。
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公开(公告)号：KR101123353B1
公开(公告)日：2012-03-13
申请号：KR1020110095291
申请日：2011-09-21
Applicant: 홍익대학교 산학협력단
CPC classification number: H03L7/0814 , H03K5/131 , H03K5/133 , H03L7/0891
Abstract: PURPOSE: A delay locked loop circuit using a feedback delay element is provided to always maintain a duty cycle in an action zone to be near 50% by using a feedback delay element as a delay circuit for a voltage controlled delay line. CONSTITUTION: A phase detector(100) receives an input clock signal and an output clock signal. The phase detector generates a phase sensing output signal according to the phase difference of two signals. A charge pump(200) generates a control voltage for controlling a voltage controlled delay line by receiving a phase sensing output signal which is outputted from the phase detector. A voltage controlled delay line(300) is composed of a plurality of FDEs(feedback delay element)(400). The voltage controlled delay line plays a role of generating an output clock signal by adding a delay time to an input clock signal.
Abstract translation: 目的：提供使用反馈延迟元件的延迟锁定环电路，通过使用反馈延迟元件作为电压控制延迟线的延迟电路，始终将动作区域的占空比保持在接近50％。 构成：相位检测器（100）接收输入时钟信号和输出时钟信号。 相位检测器根据两个信号的相位差产生相位感测输出信号。 电荷泵（200）通过接收从相位检测器输出的相位检测输出信号，产生控制电压控制延迟线的控制电压。 电压控制延迟线（300）由多个FDE（反馈延迟元件）（400）组成。 电压控制延迟线通过向输入时钟信号增加一个延迟时间起着产生输出时钟信号的作用。
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公开(公告)号：KR101900857B1
公开(公告)日：2018-09-20
申请号：KR1020170170583
申请日：2017-12-12
Applicant: 홍익대학교 산학협력단
CPC classification number: H03L7/0814 , G04F10/005 , H03L7/0818 , H03L2207/50
Abstract: 본발명은 2단타임투 디지털컨버터기반완전디지털지연고정루프회로및 그제어방법에관한것으로서, 입력클럭신호(CLK)와출력클럭신호(CLK) 사이의위상을변화시켜최종적으로입력클럭신호 (CLK)와 DQ 클럭신호(CLK) 사이의위상에러를감소시키는디지털제어지연라인; 상기디지털제어지연라인으로부터출력되는출력클럭신호(CLK)를입력받아미리정해진시간만큼지연된피드백클럭신호(CLK)를출력하여피드백클럭신호(CLK)와상기 DQ 클럭신호(CLK)의위상이같게하는레플리카클럭버퍼; 상기피드백클럭신호와입력클럭신호사이의위상차이를감소시키기위하여, 코오스락 포인트(coarse lock point)와파인락 포인트(fine lock point)를검색하여위상에러를제거하는코드를생성하는 2단타임투 디지털컨버터; 및상기 2단타임투 디지털컨버터에서출력한코오스지연코드와파인지연코드를입력으로받아시프트레지스터컨트롤러의제어신호에따라코드를저장하고, 디지털제어지연라인에적용하는시프트레지스터;를포함하는 2단타임투 디지털컨버터기반완전디지털지연고정루프회로및 그제어방법이제공된다.
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公开(公告)号：KR101248718B1
公开(公告)日：2013-04-02
申请号：KR1020120031894
申请日：2012-03-28
Applicant: 홍익대학교 산학협력단
CPC classification number: H03K5/00006 , H03K5/1534 , H03L7/0814
Abstract: PURPOSE: A delay synchronization loop based frequency multiplication device and a frequency multiplication method are provided to prevent performance degradation due to an initial bias time. CONSTITUTION: A frequency multiplication device(601) includes a delay unit(603), a provision unit(605), and a recovery unit(606). The delay unit generates an output clock by delaying an input clock of the frequency multiplication device by a delay time. The recovery unit detects generation of harmonic lock of the frequency multiplication device and recovers harmonic lock. The provision unit provides a pulse to multiply a frequency of the frequency multiplication unit. [Reference numerals] (602) Selection unit; (603) Delay unit; (604) Control unit; (605) Provision unit; (606) Recovery unit; (607) Sensing unit; (608) Comparison unit; (609) Generating unit; (AA) Input signal; (BB) Output signal;
Abstract translation: 目的：提供基于延迟同步环路的倍频装置和倍频方法，以防止初始偏置时间引起的性能下降。 构成：倍频装置（601）包括延迟单元（603），提供单元（605）和恢复单元（606）。 延迟单元通过将倍频装置的输入时钟延迟延迟时间来产生输出时钟。 恢复单元检测倍频装置的谐波锁定的产生并恢复谐波锁定。 提供单元提供脉冲以乘以倍频单元的频率。 （附图标记）（602）选择单元; （603）延迟单位; （604）控制单元; （605）拨备单位; （606）回收单位; （607）感应单元; （608）比较单位; （609）发电机组; （AA）输入信号; （BB）输出信号;
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