公开(公告)号：EP2823543B1

公开(公告)日：2016-10-05

申请号：EP13710818.9

申请日：2013-03-11

Applicant: ABB Schweiz AG

Inventor： HILLBERG, Claes ,  TRAXLER-SAMEK, Georg ,  STEIMER, Peter

IPC: H02H7/04

CPC classification number: F03B13/06 ,  F01D19/00 ,  H02H3/02 ,  H02H7/04 ,  H02J3/36 ,  H02J3/42 ,  H02K7/1807 ,  H02M7/483 ,  H02P1/52 ,  H02P9/00 ,  H02P9/04 ,  H02P9/08 ,  H02P25/022 ,  H02P25/024 ,  H02P27/14 ,  Y02E60/17 ,  Y02P80/116

公开(公告)号：EP1932231A2

公开(公告)日：2008-06-18

申请号：EP06790915.0

申请日：2006-09-29

Applicant: ABB Schweiz AG

Inventor： PONNALURI, Srinivas ,  STEIMER, Peter

IPC: H02M7/48

CPC classification number: H02M7/493

Abstract: The control means of each converter unit produces an output voltage based on reference signals (u* d , u* q ) that are generated from the active and reactive components (P, Q) of each converters output power. A first reference signal for a reactive component of the output voltage (u* q ) is set to zero, thus regulating the reactive component of the output voltage to zero. Therefore, only the active component is contributing to the actual output voltage. The reference signal for the active component of the output voltage (u* d ) is produced based on the active power component (P) with an active power vs. active voltage droop. To synchronize the frequencies of all converter units a reactive power vs. frequency droop is introduced for each converter unit, regulating the frequency based on changes in the reactive power component (Q) of each converter unit. Since the control means of each converter unit produces its reference signals based on the converter units own reactive and active power output, no communication is necessary between the various converter units operating in parallel. Converter units can therefore be placed anywhere without communication.

Abstract translation: 每个转换器单元的控制装置基于从每个转换器输出功率的有功和无功分量（P，Q）产生的参考信号（u * d，u * q）产生输出电压。 将输出电压（u * q）的无功分量的第一参考信号设置为零，从而将输出电压的无功分量调整为零。 因此，只有有源元件有助于实际的输出电压。 基于具有有功功率与有功电压下降的有功功率分量（P）产生输出电压（u * d）的有源分量的参考信号。 为了同步所有转换器单元的频率，为每个转换器单元引入无功功率与频率下降，基于每个转换器单元的无功功率分量（Q）的变化来调节频率。 由于每个转换器单元的控制装置基于具有无功和有功功率输出的转换器单元产生其参考信号，所以在并行操作的各种转换器单元之间不需要通信。 因此，转换器单元可以放置在任何地方，无需通信。

公开(公告)号：EP3306663A1

公开(公告)日：2018-04-11

申请号：EP16192299.2

申请日：2016-10-05

Applicant: ABB Schweiz AG

Inventor： LIU, Chunlei ,  RAHIMO, Munaf ,  STEIMER, Peter

IPC: H01L23/62 ,  H01L23/051 ,  H01L25/07

CPC classification number: H01L23/34 ,  H01L23/051 ,  H01L23/492 ,  H01L23/5252 ,  H01L23/62 ,  H01L24/72 ,  H01L25/072

Abstract: A semiconductor module (10) comprises a semiconductor chip (12) comprising a Si base layer (14) and a SiC epitaxy layer (16) on the Si base layer (14), the SiC epitaxy layer (16) comprising a semiconductor element (17); an electrical conducting top layer (Mo) (24) for providing an electrical contact of the semiconductor module (10) on a side of the SiC epitaxy layer (16); an electrical conducting bottom layer (Mo) (22) for providing an electrical contact of the semiconductor module (10) on a side of the Si base layer (14); and a failure mode layer (26, 26a, 26b) in contact with a top and/or bottom surface (18, 20) of the semiconductor chip (12) and arranged between the top layer (24) and the bottom layer (22), the failure mode layer (26, 26a, 26b) comprising a metal material (Al, Cu, Ag, Au) (27) adapted for forming a conducting path with the Si base layer (14), for example for forming a eutectic alloy with the Si base layer (14), to short-circuit the semiconductor module (10). The failure mode layer (26, 26b) at the bottom surface (20) of the semiconductor chip (12) may be coated to a core (30) of the bottom layer (22).

Abstract translation: 半导体模块（10）包括在Si基底层（14）上包括Si基底层（14）和SiC外延层（16）的半导体芯片（12），SiC外延层（16）包括半导体元件 17）; 用于在所述SiC外延层（16）的一侧上提供所述半导体模块（10）的电接触的导电顶层（Mo）（24）; 用于在所述Si基底层（14）的一侧上提供所述半导体模块（10）的电接触的导电底层（Mo）（22）; 和与半导体芯片（12）的顶部和/或底部表面（18,20）接触并且布置在顶层（24）和底层（22）之间的故障模式层（26,26a，26b） ，所述故障模式层（26,26a，26b）包括适于与所述Si基底层（14）形成导电路径的金属材料（Al，Cu，Ag，Au）（27），例如用于形成共晶合金 与Si基极层（14）一起短路半导体模块（10）。 半导体芯片（12）的底表面（20）处的故障模式层（26,26b）可以被涂覆到底层（22）的芯（30）。

公开(公告)号：EP3123606A1

公开(公告)日：2017-02-01

申请号：EP15729109.7

申请日：2015-06-02

Applicant: ABB Schweiz AG

Inventor： STEIMER, Peter

IPC: H02M5/458

CPC classification number: H02P6/14 ,  H02M5/4585 ,  H02M7/44 ,  H02M2007/4835

Abstract: A converter comprises a first inverter for converting a first multi-phase AC voltage into a DC voltage and a second inverter for converting the DC voltage into a second multi-phase AC voltage. A method for controlling the electrical converter comprises: switching the first inverter such that a first common mode voltage is generated in the first multi-phase AC voltage; switching the second inverter such that a second common mode voltage is generated in the second multi-phase AC voltage, wherein the first common mode voltage and the second common mode voltage are synchronized such that the first common mode voltage and the second common mode voltage cancel each other at least partially.

Abstract translation: A转换器包括用于将第一多相AC电压转换为DC电压的第一反相器和用于将DC电压转换为第二多相AC电压的第二反相器。 一种用于控制电转换器的方法，包括：切换第一反相器，使得在第一多相AC电压中产生第一共模电压; 切换第二反相器使得在第二多相AC电压中产生第二共模电压，其中第一共模电压和第二共模电压被同步，使得第一共模电压和第二共模电压抵消 彼此至少部分。

公开(公告)号：EP1647089A1

公开(公告)日：2006-04-19

申请号：EP04738029.0

申请日：2004-06-24

Applicant: ABB Schweiz AG

Inventor： STEIMER, Peter

IPC: H02M7/48

CPC classification number: H02M7/483 ,  H02M2007/4835

Abstract: A rectifier circuit for at least one phase (R, S, T) is disclosed, which includes a first vector group system (1), provided for each phase (R, S, T), comprising a first main vector group (4), formed by a power semiconductor switch and a capacitor (3), connected to the power semiconductor switch (2) and with at least one intermediate group (7), formed by two serially-connected controlled power semiconductor switches (5) and a capacitor (6), said intermediate group(s) (7) being connected to the first main vector group (4). The first vector group system further comprises a second main vector group (9), formed by a power semiconductor switch (8), whereby the or an intermediate group (7) is connected to the second main vector group (9). According to the invention, the rectifier circuit may be simplified and the incidence of faults reduced, whereby the power semiconductor switch (2), the first main vector group (4) and the power semiconductor switch (8) in the second main vector group (9) are each formed from a passive uncontrolled electronic component (11) with unidirectional current flow. To improve the storage of electrical energy with several phases (R, S, T), the first vector group systems (1) of the phases (R, S, T) are connected to each other in parallel.

公开(公告)号：EP3329585B1

公开(公告)日：2019-09-04

申请号：EP16741322.8

申请日：2016-07-21

Applicant: ABB Schweiz AG

Inventor： SCHWEIZER, Mario ,  STEIMER, Peter ,  DIJKHUIZEN, Frans

IPC: H02M7/487

公开(公告)号：EP3123606B1

公开(公告)日：2018-08-15

申请号：EP15729109.7

申请日：2015-06-02

Applicant: ABB Schweiz AG

Inventor： STEIMER, Peter

IPC: H02M5/458

CPC classification number: H02P6/14 ,  H02M5/4585 ,  H02M7/44 ,  H02M2007/4835

Abstract: A converter comprises a first inverter for converting a first multi-phase AC voltage into a DC voltage and a second inverter for converting the DC voltage into a second multi-phase AC voltage. A method for controlling the electrical converter comprises: switching the first inverter such that a first common mode voltage is generated in the first multi-phase AC voltage; switching the second inverter such that a second common mode voltage is generated in the second multi-phase AC voltage, wherein the first common mode voltage and the second common mode voltage are synchronized such that the first common mode voltage and the second common mode voltage cancel each other at least partially.

公开(公告)号：EP3329585A1

公开(公告)日：2018-06-06

申请号：EP16741322.8

申请日：2016-07-21

Applicant: ABB Schweiz AG

Inventor： SCHWEIZER, Mario ,  STEIMER, Peter ,  DIJKHUIZEN, Frans

IPC: H02M7/487

CPC classification number: H02M7/487 ,  H02M2007/4835

Abstract: A modular multi-level converter (10) for converting a DC voltage into an AC voltage comprises a first row (14) and a second row (18) of converter cells (16, 20), each converter cell (16, 20) comprising a cell capacitor (Ccell, Ccell') and semiconductor switches (34, 36, 34', 36') adapted for connecting the cell capacitor to an output of the converter cell (16, 20) and for bypassing the cell capacitor. The first row (14) of converter cells (16) interconnects a positive DC link connection point (22a) and a negative DC link connection point (22c), wherein the first row (14) of converter cells (16) comprises an upper pair and a lower pair of series-connected strings (24a, 24b, 24c, 24d) of series-connected converter cells (16), wherein the upper pair of strings (24a, 24b) connects the positive DC link connection point (22a) with a neutral DC link connection point (22b) and provides an upper intermediate connection point (26a) between the strings (24a, 24b) and the lower pair of strings (24c, 24d) connects the negative DC link connection point (22c) with the neutral DC link connection point (22b) and provides a lower intermediate connection point (26b) between the strings (24c, 24d). The second row (18) of converter cells (20) comprises a pair of strings (28a, 28b) of series-connected converter cells (20) interconnecting the upper intermediate connection point (26a) and the lower intermediate connection point (26b) and provides an AC connection point between the strings (28a, 28b). The converter cells (16) of the first row (14) have a first cell capacity (Ccell') and the converter cells (20) of the second row (18) have a second cell capacity (Ccell) higher than the first cell capacity (Ccell'). The converter cells (16) of the first row (14) have a capacitor switch (36'), which interconnects the cell capacitor (Ccell') with the outputs (38) and which has a lower current rating than a main switch (34') of the converter cells (16) of the first row (14) connected in parallel to the cell capacitor (Ccell'). The converter cells (20) of the second row (18) have a capacitor switch (36) and the current rating of the capacitor switch (36') of a converter cell (16) of the first row (14) is smaller than a current rating of the capacitor switch (36) of a converter cell (20) of the second row (18).

公开(公告)号：EP1973760B1

公开(公告)日：2009-07-22

申请号：EP06705396.7

申请日：2006-03-16

Applicant: ABB Schweiz AG

Inventor： STEIMER, Peter

IPC: B60L11/02 ,  H02K16/04

CPC classification number: B60L11/08 ,  B60L2200/26 ,  Y02T10/70 ,  Y02T10/7077

Abstract: The invention specifies a fuel/electric drive system having an internal combustion engine (1), having a generator (2) which is driven by the internal combustion engine (1) and has a first stator winding set (A), having a first rectifier (3) which is connected to the first stator winding set (A) at the AC voltage end and to a first DC voltage circuit (4) at the DC voltage end, and having a first inverter (5) which is connected to the first DC voltage circuit (4) at the DC voltage end and to a drive motor (6) at the AC voltage end. In order to increase the robustness and availability of the fuel/electric drive system, the generator (2) has a second stator winding set (B), with a second rectifier (7) being connected to the second stator winding set (B) at the AC voltage end and to a second DC voltage circuit (8) at the DC voltage end, and a second inverter (9) being connected to the second DC voltage circuit (8) at the DC voltage end and to the drive motor (6) at the AC voltage end.

公开(公告)号：EP1695434B1

公开(公告)日：2008-05-21

申请号：EP04820375.6

申请日：2004-12-13

Applicant: ABB Schweiz AG

Inventor： PONNALURI, Srinivas ,  STEINKE, Jürgen ,  STEIMER, Peter

IPC: H02M7/08 ,  H02M1/12 ,  H02J3/01 ,  H02M7/17

CPC classification number: H02M5/4585 ,  H02M7/49