公开(公告)号：WO1996016481A1

公开(公告)日：1996-05-30

申请号：PCT/US1995015129

申请日：1995-11-21

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  QUINLAN, Philip ,  DEEVY, Kenneth, T.

IPC: H03M01/76

CPC classification number: H03M1/685 ,  H03M1/765

Abstract: A differential string DAC is provided including a coarse DAC which includes a plurality of coarse resistors connected in series between first and second reference voltage leads. A positive sub-DAC includes a plurality of positive sub-DAC cells, each positive sub-DAC cell including a multitude of series-connected fine resistors. A negative sub-DAC includes a plurality of negative sub-DAC cells, each negative sub-DAC cell including a multitude of series-connected fine resistors. Each coarse resistor is electrically connected in parallel with one positive sub-DAC cell and one negative sub-DAC cell. The positive sub-DAC cell and negative sub-DAC cell are substantially symmetrically disposed about the corresponding coarse resistor. Due to the differential arrangement and symmetrical layout of the DAC, INL errors due to process gradients in one direction across the DAC are greatly reduced. Process gradients in a second orthogonal direction are not of great concern as they cause much smaller INL errors.

Abstract translation: 提供了一种差分串DAC，其包括粗略DAC，其包括串联连接在第一和第二参考电压引线之间的多个粗电阻。 正的副DAC包括多个正的sub-DAC单元，每个正的副DAC单元包括多个串联的精细电阻。 负的副DAC包括多个负的副DAC单元，每个负的Sub-DAC单元包括多个串联的精细电阻。 每个粗电阻器与一个正的副DAC电池和一个负的Sub-DAC电池并联电连接。 正的sub-DAC单元和负的sub-DAC单元基本对称地布置在相应的粗略电阻周围。 由于DAC的差分布置和对称布局，大大减少了由DAC处的一个方向上的工艺梯度引起的INL误差。 在第二正交方向上的处理梯度不是很大的关注，因为它们导致更小的INL误差。

公开(公告)号：WO1995034129A1

公开(公告)日：1995-12-14

申请号：PCT/US1995005733

申请日：1995-05-09

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GUSINOV, Alex ,  GERSTENHABER, Moshe

IPC: H03F03/30

CPC classification number: H03F3/3067

Abstract: A gain stage for use in an amplifier which provides a rail-to-rail output signal. The gain stage includes a first transistor having a base, an emitter and a collector, the base being coupled to an input signal applied to the gain stage and the emitter being coupled to a first source of operating potential; a second transistor having a base, and emitter and a collector, the collector being coupled to the collector of the first transistor for providing the output signal, the emitter being coupled to a second source of operating potential; and a third transistor having a base, an emitter and a collector, the emitter being coupled to the input signal, the base being coupled to a bias voltage, and the collector being coupled to the second operating potential and the base of the second transistor for providing a drive signal thereto allowing the output signal to swing substantially between the first and second sources of operating potential.

Abstract translation: 用于放大器的增益级，其提供轨到轨输出信号。 所述增益级包括具有基极，发射极和集电极的第一晶体管，所述基极耦合到施加到所述增益级的输入信号，所述发射极耦合到第一工作电位; 具有基极和发射极和集电极的第二晶体管，所述集电极耦合到所述第一晶体管的集电极以提供所述输出信号，所述发射极耦合到第二工作电位; 以及具有基极，发射极和集电极的第三晶体管，所述发射极耦合到所述输入信号，所述基极耦合到偏置电压，并且所述集电极耦合到所述第二工作电位和所述第二晶体管的基极， 提供驱动信号，使得输出信号基本上在第一和第二操作电源之间摆动。

公开(公告)号：WO1995030271A1

公开(公告)日：1995-11-09

申请号：PCT/US1995005238

申请日：1995-04-27

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARAVAN, Patrick, J.

IPC: H03F01/30

CPC classification number: H03F3/45479 ,  H03F1/303 ,  H03F3/45192 ,  H03F3/45475 ,  H03F3/45986 ,  H03F2203/45371 ,  H03F2203/45398 ,  H03F2203/45462 ,  H03F2203/45508 ,  H03F2203/45612 ,  H03F2203/45636 ,  H03F2203/45644

Abstract: A CMOS comparator which includes a capacitor connected in an electrical path between two amplification stages. The comparator also includes a voltage source, and a switch is provided between the voltage source and the input of the second stage. A variability of electrical parameter of the voltage source can be matched with a parameter of the amplification stage. The comparator can also include another switch between another voltage source and a third stage, with the two voltage sources providing different voltages. A comparator gain stage includes circuitry for deriving a differential current from the two voltages. Circuitry is also provided for loading the differential current to derive an amplified difference voltage. Further circuitry is provided for bypassing the loading circuitry to reduce a quiescent voltage drop associated with the loading circuitry.

Abstract translation: CMOS比较器，其包括连接在两个放大级之间的电路中的电容器。 比较器还包括电压源，并且在电压源和第二级的输入之间提供开关。 电压源的电参数的变化可以与放大级的参数匹配。 比较器还可以包括在另一个电压源和第三级之间的另一个开关，两个电压源提供不同的电压。 比较器增益级包括用于从两个电压导出差分电流的电路。 还提供电路用于加载差分电流以导出放大的差分电压。 提供了进一步的电路来绕过负载电路以减少与负载电路相关联的静态电压降。

公开(公告)号：WO1995002923A1

公开(公告)日：1995-01-26

申请号：PCT/US1994007334

申请日：1994-06-29

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  MUECK, Michael ,  FERGUSON, Paul, F., Jr.

IPC: H03G01/04

CPC classification number: H03G1/04 ,  H03M1/1019 ,  H03M1/66 ,  H03M3/38 ,  H03M3/51

Abstract: A system includes a digital-to-analog converter circuit and a calibration circuit. The digital-to-analog converter circuit includes a gain control circuit providing volume adjustment. The system includes a calibration mode and a normal mode of operation. During calibration, a correction value associated with the gain control circuit is measured by the calibration circuit and stored. During normal operation, the stored correction value is combined with the input before provision of the same to the DAC circuit such that, for a predetermined input of midscale code, the desired system output remains constant despite any change in the volume setting of the gain control circuit.

Abstract translation: 系统包括数模转换器电路和校准电路。 数模转换器电路包括提供音量调节的增益控制电路。 该系统包括校准模式和正常操作模式。 在校准期间，与增益控制电路相关联的校正值由校准电路测量并存储。 在正常操作期间，将存储的校正值与其提供给DAC电路之前的输入组合，使得对于预定的中间码的输入，期望的系统输出保持恒定，尽管增益控制的音量设置有任何改变 电路。

公开(公告)号：WO1994024628A1

公开(公告)日：1994-10-27

申请号：PCT/US1994004455

申请日：1994-04-22

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas

IPC: G06F13/00

CPC classification number: G06F13/4217 ,  G06F13/1615

Abstract: A multi-phase, multi-access pipeline memory system includes a numer, n, of processors (14, 16); a pipeline memory (12) including a latch (28); and a bus (30, 32, 34, 36) for interconnecting the processors and pipeline memory; a clock circuit (18) responsive to a system clock signal (20) into n phases for providing multiple clock signals (22, 24, 26) corresponding to the n phases of the system clock signal (20) for operating each processor (14, 16) to allow data and address to be transferred only during its assigned phase thereby enabling the memory (12) and each processor (14, 16) to operate at the system clock rate while allowing n accesses to the memory (12) during each system clock signal period, one access for each processor (14, 16).

Abstract translation: 一种多相多通道流水线存储器系统，包括：n，n个处理器（14,16）; 包括闩锁（28）的管线存储器（12）; 以及用于互连处理器和流水线存储器的总线（30,32,34,36）; 响应于系统时钟信号（20）的时钟电路（18）成n相，用于提供对应于系统时钟信号（20）的n个相位的多个时钟信号（22,24,26），用于操作每个处理器 16）允许仅在其分配阶段期间传送数据和地址，从而使得存储器（12）和每个处理器（14,16）能够以系统时钟速率工作，同时在每个系统期间允许对存储器（12）的n次访问 时钟信号周期，每个处理器（14,16）一次访问。

公开(公告)号：WO1994023494A1

公开(公告)日：1994-10-13

申请号：PCT/US1994003785

申请日：1994-04-06

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  KWAN, Tom, W. ,  FERGUSON, Paul, F., Jr. ,  LEE, Wai, L.

IPC: H03H19/00

CPC classification number: H03H19/004

Abstract: A biquad switched capacitor filter is preferably utilized as the output filter in a sigma delta digital-to-analog converter. The switched capacitor filter uses a cross-coupled switched capacitor circuit which delivers charge to the capacitors on both phases of the clock. As a result, the sizes of the capacitors can be reduced by a factor of two, while delivering the same charge as a single sampling circuit. By using the cross-coupled switching circuit everywhere in the filter, the sensitivity to capacitor mismatches is substantially reduced. The clock phases applied to the stages of the filter are alternated so that there is a one clock cycle delay around each loop containing two filter stages, thereby insuring the stability of the filter.

Abstract translation: 双倍开关电容滤波器优选地用作Σ-Δ数模转换器中的输出滤波器。 开关电容滤波器使用交叉耦合开关电容器电路，其在时钟的两相上向电容器递送电荷。 结果，电容器的尺寸可以减少2倍，同时提供与单个采样电路相同的电荷。 通过在滤波器中的任何地方使用交叉耦合开关电路，电容器失配的灵敏度大大降低。 施加到滤波器的级的时钟相位交替，使得在包含两个滤波器级的每个回路周围有一个时钟周期延迟，从而确保滤波器的稳定性。

公开(公告)号：WO1993025001A1

公开(公告)日：1993-12-09

申请号：PCT/US1993004868

申请日：1993-05-24

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  JORDAN, Edward, Perry

IPC: H03K07/08

CPC classification number: H03K7/08

Abstract: An anti-false triggering system for a pulse width modulation system includes a ramp generator (108) for generating a ramp signal having a ramp portion and a rest portion; a latch enable signal generator (110) for providing a latch enable signal only during the ramp portion; and a pulse edge modulator (106) responsive to the ramp portion for providing a pulse width modulated signal with at least one of its edges modulated, the pulse edge modulator (106) being enabled by the latch enable signal only during the ramp portion for suppressing false triggering during the rest portion of the ramp signal.

公开(公告)号：WO1993016493A1

公开(公告)日：1993-08-19

申请号：PCT/US1993001233

申请日：1993-02-11

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  REYNOLDS, David

IPC: H01L23/64

CPC classification number: H01L23/647 ,  H01L23/64 ,  H01L24/49 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An integrated circuit chip is provided with at least a component on it. The component may be, for instance, an analog-to-digital converter or a digital-to-analog converter. The component has at least one connection leading off the chip to facilitate communication between the component and an external device. The chip additionally includes an active element, such as a variable resistor, for compensating for non-ideal electrical impedance experienced by signals at said connection.

Abstract translation: 集成电路芯片上至少提供有一个部件。 该组件可以是例如模数转换器或数模转换器。 该组件具有至少一个引出芯片的连接，以促进组件和外部设备之间的通信。 该芯片还包括有源元件，例如可变电阻器，用于补偿由所述连接处的信号所经历的非理想电阻抗。

公开(公告)号：WO1992003740A1

公开(公告)日：1992-03-05

申请号：PCT/US1991005851

申请日：1991-08-16

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  SHERMAN, Steven, J. ,  BROKAW, A., Paul ,  TSANG, Robert, W., K. ,  CORE, Theresa

IPC: G01P15/125

CPC classification number: B81C99/004 ,  B81B2201/0235 ,  G01P15/0802 ,  G01P15/125 ,  G01P15/131 ,  G01P2015/0814

Abstract: An accelerometer comprising a microfabricated acceleration sensor and monolithically fabricated signal conditioning circuitry. The sensor comprises a differential capacitor arrangement formed by a pair of capacitors. Each capacitor has two electrodes, one of which it shares electrically in common with the other capacitor. One of the electrodes (e.g., the common electrode) is movable and one of the electrodes is stationary in response to applied acceleration. The electrodes are all formed of polysilicon members suspended above a silicon substrate. Each of the capacitors is formed of a plurality of pairs of electrode segments electrically connected in parallel and, in the case of the movable electrodes, mechanically connected to move in unison. When the substrate is accelerated, the movable electrodes move such that the capacitance of one of the capacitors increases, while that of the other capacitor decreases. The two capacitors are connected to signal conditioning circuitry which converts this differential capacitance into a corresponding voltage. Both open loop and force-balance operation are shown.

Abstract translation: 一种包括微加速度加速度传感器和单片制造的信号调节电路的加速度计。 传感器包括由一对电容器形成的差分电容器装置。 每个电容器具有两个电极，其中一个电极与另一个电容器共用。 电极（例如，公共电极）中的一个可移动，并且电极中的一个响应于所施加的加速度而是静止的。 电极全部由悬浮在硅衬底上的多晶硅构件形成。 每个电容器由多对并联电连接的电极段形成，并且在可移动电极的情况下，机械连接以一致地移动。 当基板被加速时，可移动电极移动，使得一个电容器的电容增加，而另一个电容器的电容减小。 两个电容器连接到信号调节电路，该电路将该差分电容转换成相应的电压。 显示开环和力平衡操作。

公开(公告)号：WO1991007825A2

公开(公告)日：1991-05-30

申请号：PCT/US1990006790

申请日：1990-11-19

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  BROKAW, A., Paul

IPC: H03M01/06

CPC classification number: H03M1/089 ,  H03M1/785

Abstract: A termination circuit for an R-2R ladder network for producing weighted currents, the 2R terminating resistor of the ladder being connected to an excitation source voltage which is 2(kT/q)ln2 closer to the supply voltage than the emitter of the current source in the last (i.e., least significant) leg of the ladder. The excitation source is fabricated with just one type of bipolar transistor and does not require an amplifier or frequency compensation capacitor(s). The excitation source is a simple circuit requiring only five transistors, at least one of which has an emitter area which is a multiple of the emitter areas of the current source transistors. The base-emitter voltages of the transistors in the excitation source are connected in a voltage loop that goes from a voltage VLSB at the emitter of the current source transistor connected to the least significant ladder network shunt resistor to a voltage, Vt, which would be equal to VLSB, if all six transistors in the loop had the same emitter area, but which deviates therefrom by 2(kT/q)ln2 due to the differences in the emitter areas.