公开(公告)号：HK1165878A1

公开(公告)日：2012-10-12

申请号：HK12106421

申请日：2012-07-03

Applicant: APPLE INC

Inventor： VON KAENEL VINCENT R

IPC: G06F20060101

Abstract: In one embodiment, an integrated circuit (10) includes a self calibration unit (16) configured to iterate a test on a logic circuit (14) in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit.

公开(公告)号：AU2010208458A1

公开(公告)日：2011-08-04

申请号：AU2010208458

申请日：2010-01-22

Applicant: APPLE INC

Inventor： VON KAENEL VINCENT R

IPC: G06F1/32

Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

公开(公告)号：WO2010088155A2

公开(公告)日：2010-08-05

申请号：PCT/US2010021840

申请日：2010-01-22

Applicant: APPLE INC ,  VON KAENEL VINCENT R

Inventor： VON KAENEL VINCENT R

IPC: G06F1/32

CPC classification number: H03K19/0008 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

Abstract translation: 在一个实施例中，集成电路包括自校准单元，其被配置为在分别较低的电源电压幅度下对集成电路中的逻辑电路进行测试，直到测试失败为止。 测试通过的最低电源电压幅度用于为集成电路产生所请求的电源电压幅度。 在一个实施例中，集成电路包括物理分布在集成电路的区域上的逻辑门的串联连接，以及测量单元，被配置为将逻辑跃迁发射到该系列中，并且检测在该系列的输出处的对应转变。 发射和检测之间的时间量用于请求集成电路的电源电压幅值。

公开(公告)号：WO2013012634A3

公开(公告)日：2014-05-08

申请号：PCT/US2012046248

申请日：2012-07-11

Applicant: APPLE INC ,  ZHAI JUN ,  VON KAENEL VINCENT R

Inventor： ZHAI JUN ,  VON KAENEL VINCENT R

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2224/4824 ,  H01L2224/81815 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15153 ,  H01L2924/15321 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module.

Abstract translation: 具有安装在基板的相对侧上的两个或多个集成电路管芯的半导体器件模块。 集成电路管芯通过使用表面安装连接来安装，例如使用导电凸块实现的倒装芯片连接。 系统可以包括一个或多个当前的半导体器件模块，并且在一些情况下还可以包括其他模块，诸如系统模块。