中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.021 seconds)

    Dynamic voltage and frequency management
    3.
    发明专利
    Dynamic voltage and frequency management 有权
    动态电压和频率管理

    公开(公告)号：JP2013031207A

    公开(公告)日：2013-02-07

    申请号：JP2012200727

    申请日：2012-09-12

    Applicant: Apple Inc ,  アップル インコーポレイテッド

    Inventor： VON KAENEL VINCENT R

    IPC: H03K19/00

    CPC classification number: H03K19/0008 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: PROBLEM TO BE SOLVED: To determine supply voltage magnitudes that ensure correct operation at the given frequency across all acceptable variations in the manufacturing process and all permissible operating temperatures.SOLUTION: An integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower requested supply voltage magnitudes until the test fails. A lowest requested supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. The integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

    Abstract translation: 要解决的问题：确定在制造过程中所有可接受的变化和所有允许的工作温度下确保在给定频率下正确工作的电源电压幅值。 解决方案：集成电路包括自校准单元，其被配置为在分别较低的请求电源电压幅度下对集成电路中的逻辑电路进行测试，直到测试失败为止。 测试通过的最低要求电源电压幅度用于为集成电路产生所请求的电源电压幅度。 集成电路包括物理分布在集成电路的区域上的逻辑门的串联连接，以及测量单元，被配置为将逻辑转换发射到串联中并检测在该系列的输出处的相应转变。 发射和检测之间的时间量用于请求集成电路的电源电压幅值。 版权所有（C）2013，JPO＆INPIT

    Dynamic voltage and frequency management
    4.
    发明专利
    Dynamic voltage and frequency management 未知

    公开(公告)号：AU2010208458B2

    公开(公告)日：2012-02-02

    申请号：AU2010208458

    申请日：2010-01-22

    Applicant: APPLE INC

    Inventor： VON KAENEL VINCENT R

    IPC: G06F1/32

    Abstract: In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

    Dynamic voltage and frequency management
    5.
    发明专利
    Dynamic voltage and frequency management 未知

    公开(公告)号：AU2011226847A1

    公开(公告)日：2011-10-13

    申请号：AU2011226847

    申请日：2011-09-23

    Applicant: APPLE INC

    Inventor： VON KAENEL VINCENT R

    IPC: G06F1/32

    Abstract: A~n integrated circuit includes a logic circuit, a local power manager coupled to the logic circuit, and a self calibration unit. The local power manager is configured to transmit an indication of a requested supply voltage magnitude to an external power supply. The self calibration unit is configured to execute a test on the logic circuit, and to iterate the test at respectively lower requested supply voltage magnitudes until the test fails. A lowest requested supply voltage magnitude at which the test passes is used to generate the requested supply voltage magnitude for operation of the integrated circuit. The self calibration unit is further configured to iterate the test and determine the lowest requested supply voltage magnitude in response to the logic circuit executing a different workload.

    DELAY LOCKED LOOP INCLUDING A MECHANISM FOR REDUCING LOCK TIME
    7.
    发明专利
    DELAY LOCKED LOOP INCLUDING A MECHANISM FOR REDUCING LOCK TIME 未知

    公开(公告)号：HK1169222A1

    公开(公告)日：2013-01-18

    申请号：HK12109708

    申请日：2012-10-03

    Applicant: APPLE INC

    Inventor： TRIVEDI PRADEEP R ,  VON KAENEL VINCENT R

    IPC: H03L20060101

    Abstract: A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.

    DYNAMIC LEAKAGE CONTROL FOR MEMORY ARRAYS
    8.
    发明专利
    DYNAMIC LEAKAGE CONTROL FOR MEMORY ARRAYS 未知

    公开(公告)号：HK1164531A1

    公开(公告)日：2012-09-21

    申请号：HK12104747

    申请日：2012-05-15

    Applicant: APPLE INC

    Inventor： SHIU SHINYE ,  VON KAENEL VINCENT R

    IPC: G11C20060101

    Abstract: A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.

    Double-sided flip chip package
    9.
    发明专利
    Double-sided flip chip package 未知

    公开(公告)号：AU2012204142A1

    公开(公告)日：2013-02-07

    申请号：AU2012204142

    申请日：2012-07-12

    Applicant: APPLE INC

    Inventor： ZHAI JUN ,  VON KAENEL VINCENT R

    IPC: H01L21/44

    Abstract: Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. 5 Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module. 110a 22110b 200b 20a100 130 { 130 VVVV VVu .VVV VVVVVV VVVVVV VV VVVV VVV 200bor 3 100 110b 1)3 130 110a 210a 200a 210c 200c 130 110a 130 o 0 0 0 0 0 0 o 0 0 120a 120c o 0 0 0 0 0 0 0 0 0 0 0 io o o lo o o 0 o 0~l 0 o00 01 lo o o o10 o oi o l o0 0 lo o o ol lo o o ol 0 o 10 0 0 01 10 0 0 o o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Patent Agency Ranking