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公开(公告)号：US10901920B2
公开(公告)日：2021-01-26
申请号：US16380300
申请日：2019-04-10
Applicant: Apple Inc.
Inventor： Jainam A. Shah , Jeremy C. Andrus , Daniel A. Chimene , Kushal Dalmia , Pierre Habouzit , James M. Magee , Marina Sadini , Daniel A. Steffen
Abstract: One embodiment provides for a computer-implemented method comprising instantiating a synchronization primitive to control access to a resource, acquiring the synchronization primitive at a first thread, the first thread having a first priority, associating a turnstile with the synchronization primitive, setting an inheritor of the turnstile to the first thread, attempting to acquire the synchronization primitive at a second thread while the synchronization primitive is held by the first thread, the second thread having a second priority, adding the second thread to a wait queue of the turnstile; and in response to determining that the second priority is higher than the first priority, increasing the priority of the first thread to the second priority.
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公开(公告)号：US20180349176A1
公开(公告)日：2018-12-06
申请号：US15870763
申请日：2018-01-12
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol
CPC classification number: G06F9/505 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/329 , G06F1/3296 , G06F9/268 , G06F9/30145 , G06F9/3851 , G06F9/3891 , G06F9/4856 , G06F9/4881 , G06F9/4893 , G06F9/5044 , G06F9/5094 , G06F9/54 , G06F2209/501 , G06F2209/5018 , G06F2209/509
Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
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公开(公告)号：US20170269967A1
公开(公告)日：2017-09-21
申请号：US15444186
申请日：2017-02-27
Applicant: Apple Inc.
Inventor： Daniel A. Steffen , Matthew W. Wright , Russell A. Blaine , Daniel A. Chimene , Kevin J. Van Vechten , Thomas B. Duffy
CPC classification number: G06F9/4893 , G06F9/4881 , G06F9/5038 , G06F2209/5021 , Y02D10/22
Abstract: In one embodiment, tasks executing on a data processing system can be associated with a Quality of Service (QoS) classification that is used to determine the priority values for multiple subsystems of the data processing system. The QoS classifications are propagated when tasks interact and the QoS classes are interpreted a multiple levels of the system to determine the priority values to set for the tasks. In one embodiment, one or more sensors coupled with the data processing system monitor a set of system conditions that are used in part to determine the priority values to set for a QoS class.
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公开(公告)号：US09348645B2
公开(公告)日：2016-05-24
申请号：US14576917
申请日：2014-12-19
Applicant: Apple Inc.
Inventor： James Michael Magee , Russell A. Blaine , Daniel A. Chimene , James McIlree , Vishal Patel , Daniel Andreas Steffen , Kevin James Van Vechten
CPC classification number: G06F9/4881 , G06F1/3206 , G06F1/3287 , G06F9/461 , G06F9/468 , G06F9/4818 , G06F9/50 , G06F9/52 , G06F9/545 , G06F2209/484 , G06F2209/485 , Y02D10/171 , Y02D10/24
Abstract: A method and an apparatus for priority donations among different processes are described. A first process running with a first priority may receive a request from a second process running with a second priority to perform a data processing task for the second process. A dependency relationship may be identified between the first process and a third process running with a third priority performing separate data processing task. The dependency relationship may indicate that the data processing task is to be performed via the first process subsequent to completion of the separate data processing task via the third process. The third process may be updated with the second priority to complete the separate data processing task. The first process may perform the data processing task with the second priority for the second process.
Abstract translation: 描述了用于不同处理之间的优先捐赠的方法和装置。 以第一优先级运行的第一进程可以从具有第二优先级的第二进程接收请求，以执行第二进程的数据处理任务。 可以在第一进程和执行分开的数据处理任务的第三优先级运行的第三进程之间识别依赖关系。 依赖关系可以指示经由第三处理完成单独的数据处理任务之后，经由第一处理执行数据处理任务。 可以用第二优先级来更新第三进程以完成单独的数据处理任务。 第一进程可以执行具有第二进程的第二优先级的数据处理任务。
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公开(公告)号：US20150347189A1
公开(公告)日：2015-12-03
申请号：US14292687
申请日：2014-05-30
Applicant: Apple Inc.
Inventor： DANIEL A. STEFFEN , Matthew W. Wright , Russell A. Blaine, JR. , Daniel A. Chimene , Kevin J. Van Vechten , Thomas B. Duffy
IPC: G06F9/48
CPC classification number: G06F9/4893 , G06F9/4881 , G06F9/5038 , G06F2209/5021 , Y02D10/22
Abstract: In one embodiment, tasks executing on a data processing system can be associated with a Quality of Service (QoS) classification that is used to determine the priority values for multiple subsystems of the data processing system. The QoS classifications are propagated when tasks interact and the QoS classes are interpreted a multiple levels of the system to determine the priority values to set for the tasks. In one embodiment, one or more sensors coupled with the data processing system monitor a set of system conditions that are used in part to determine the priority values to set for a QoS class.
Abstract translation: 在一个实施例中，在数据处理系统上执行的任务可以与用于确定数据处理系统的多个子系统的优先级值的服务质量（QoS）分类相关联。 当任务交互并且QoS类被解释为系统的多个级别以确定为任务设置的优先级值时，QoS分类被传播。 在一个实施例中，与数据处理系统耦合的一个或多个传感器监视在一部分中用于确定为QoS类设置的优先级值的一组系统条件。
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Patent Agency Ranking
公开(公告)号：US20150347177A1
公开(公告)日：2015-12-03
申请号：US14576917
申请日：2014-12-19
Applicant: Apple Inc.
Inventor： James Michael Magee , Russell A. Blaine , Daniel A. Chimene , James McIlree , Vishal Patel , Daniel Andreas Steffen , Kevin James Van Vechten
IPC: G06F9/48
CPC classification number: G06F9/4881 , G06F1/3206 , G06F1/3287 , G06F9/461 , G06F9/468 , G06F9/4818 , G06F9/50 , G06F9/52 , G06F9/545 , G06F2209/484 , G06F2209/485 , Y02D10/171 , Y02D10/24
Abstract: A method and an apparatus for priority donations among different processes are described. A first process running with a first priority may receive a request from a second process running with a second priority to perform a data processing task for the second process. A dependency relationship may be identified between the first process and a third process running with a third priority performing separate data processing task. The dependency relationship may indicate that the data processing task is to be performed via the first process subsequent to completion of the separate data processing task via the third process. The third process may be updated with the second priority to complete the separate data processing task. The first process may perform the data processing task with the second priority for the second process.
Abstract translation: 描述了用于不同处理之间的优先捐赠的方法和装置。 以第一优先级运行的第一进程可以从具有第二优先级的第二进程接收请求，以执行第二进程的数据处理任务。 可以在第一进程和执行分开的数据处理任务的第三优先级运行的第三进程之间识别依赖关系。 依赖关系可以指示经由第三处理完成单独的数据处理任务之后，经由第一处理执行数据处理任务。 可以用第二优先级来更新第三进程以完成单独的数据处理任务。 第一进程可以执行具有第二进程的第二优先级的数据处理任务。
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公开(公告)号：US11940931B2
公开(公告)日：2024-03-26
申请号：US17141914
申请日：2021-01-05
Applicant: Apple Inc.
Inventor： Jainam A. Shah , Jeremy C. Andrus , Daniel A. Chimene , Kushal Dalmia , Pierre Habouzit , James M. Magee , Marina Sadini , Daniel A. Steffen
CPC classification number: G06F12/1466 , G06F9/4881 , G06F9/5038 , G06F9/52 , G06F9/526 , G06F9/541 , G06F9/545 , G06F12/0842 , G06F2209/5011
Abstract: A turnstile OS primitive is provided that enables support for owner tracking and waiting. The turnstile primitive enables a common framework that can be adopted across multiple different types of synchronization primitives to provide a common service for priority boosting and wait queuing. A turnstile can also provide a mechanism to enable a turnstile to block on another turnstile, allowing multi-hop priority boosting within a chain of multiple blocking turnstiles.
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公开(公告)号：US11360820B2
公开(公告)日：2022-06-14
申请号：US15996469
申请日：2018-06-02
Applicant: Apple Inc.
Inventor： John G. Dorsey , Daniel A. Chimene , Andrei Dorofeev , Bryan R. Hinch , Evan M. Hoke , Aditya Venkataraman
IPC: G06F9/50 , G06F9/48 , G06F1/3234 , G06F1/329 , G06F1/3296 , G06F9/38 , G06F9/26 , G06F9/54 , G06F1/20 , G06F1/324 , G06F1/3206 , G06F9/30
Abstract: Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.
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公开(公告)号：US11086800B2
公开(公告)日：2021-08-10
申请号：US16882087
申请日：2020-05-22
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , Joseph R. Auricchio , Russell A. Blaine , Daniel A. Chimene , Simon M. Douglas , Landon J. Fuller , Yevgen Goryachok , John K. Kim-Biggs , Arnold S. Liu , James M. Magee , Daniel A. Steffen , Roberto G. Yepez
Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.
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20.发明授权公开(公告)号：US11080095B2
公开(公告)日：2021-08-03
申请号：US15870766
申请日：2018-01-12
Applicant: Apple Inc.
Inventor： Jeremy C. Andrus , John G. Dorsey , James M. Magee , Daniel A. Chimene , Cyril de la Cropte de Chanterac , Bryan R. Hinch , Aditya Venkataraman , Andrei Dorofeev , Nigel R. Gamble , Russell A. Blaine , Constantin Pistol
IPC: G06F9/46 , G06F9/50 , G06F9/48 , G06F1/3234 , G06F1/329 , G06F1/3296 , G06F9/38 , G06F9/26 , G06F9/54 , G06F1/20 , G06F1/324 , G06F1/3206 , G06F9/30
Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.
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