公开(公告)号：US11579934B2

公开(公告)日：2023-02-14

申请号：US17208928

申请日：2021-03-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US10908954B2

公开(公告)日：2021-02-02

申请号：US15444186

申请日：2017-02-27

Applicant: Apple Inc.

Inventor： Daniel A. Steffen ,  Matthew W. Wright ,  Russell A. Blaine ,  Daniel A. Chimene ,  Kevin J. Van Vechten ,  Thomas B. Duffy

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

Abstract: In one embodiment, tasks executing on a data processing system can be associated with a Quality of Service (QoS) classification that is used to determine the priority values for multiple subsystems of the data processing system. The QoS classifications are propagated when tasks interact and the QoS classes are interpreted a multiple levels of the system to determine the priority values to set for the tasks. In one embodiment, one or more sensors coupled with the data processing system monitor a set of system conditions that are used in part to determine the priority values to set for a QoS class.

公开(公告)号：US20150347192A1

公开(公告)日：2015-12-03

申请号：US14290791

申请日：2014-05-29

Applicant: Apple Inc.

Inventor： Russell A. Blaine ,  Daniel A. Chimene ,  Shantonu Sen ,  James M. Magee

IPC: G06F9/50

CPC classification number: G06F9/5027 ,  G06F9/4881 ,  G06F2209/5021

Abstract: Techniques for scheduling threads for execution in a data processing system are described herein. According to one embodiment, in response to a request for executing a thread, a scheduler of an operating system of the data processing system accesses a global run queue to identify a global run entry associated with the highest process priority. The global run queue includes multiple global run entries, each corresponding to one of a plurality of process priorities. A group run queue is identified based on the global run entry, where the group run queue includes multiple threads associated with one of the processes. The scheduler dispatches one of the threads that has the highest thread priority amongst the threads in the group run queue to one of the processor cores of the data processing system for execution.

Abstract translation: 在这里描述了用于调度用于在数据处理系统中执行的线程的技术。 根据一个实施例，响应于执行线程的请求，数据处理系统的操作系统的调度器访问全局运行队列以识别与最高进程优先级相关联的全局运行条目。 全局运行队列包括多个全局运行条目，每个条目对应于多个进程优先级中的一个。 基于全局运行条目识别组运行队列，其中组运行队列包括与其中一个进程相关联的多个线程。 调度程序将组运行队列中的线程中具有最高线程优先级的一个线程调度到数据处理系统的一个处理器核心以执行。

公开(公告)号：US11860796B2

公开(公告)日：2024-01-02

申请号：US17397966

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  Joseph R. Auricchio ,  Russell A. Blaine ,  Daniel A. Chimene ,  Simon M. Douglas ,  Landon J. Fuller ,  Yevgen Goryachok ,  John K. Kim-Biggs ,  Arnold S. Liu ,  James M. Magee ,  Daniel A. Steffen ,  Roberto G. Yepez

IPC: G06F9/54 ,  G06F21/57 ,  G06F13/10 ,  G06F13/40 ,  G06F9/445 ,  G06F13/16

CPC classification number: G06F13/102 ,  G06F9/44505 ,  G06F9/545 ,  G06F9/546 ,  G06F13/1673 ,  G06F13/4072

Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

公开(公告)号：US20210318909A1

公开(公告)日：2021-10-14

申请号：US17208928

申请日：2021-03-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20200379925A1

公开(公告)日：2020-12-03

申请号：US16882087

申请日：2020-05-22

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  Joseph R. Auricchio ,  Russell A. Blaine ,  Daniel A. Chimene ,  Simon M. Douglas ,  Landon J. Fuller ,  Yevgen Goryachok ,  John K. Kim-Biggs ,  Arnold S. Liu ,  James M. Magee ,  Daniel A. Steffen ,  Roberto G. Yepez

IPC: G06F13/10 ,  G06F13/40 ,  G06F9/54 ,  G06F9/445 ,  G06F13/16

Abstract: Embodiments described herein provide techniques to manage drivers in a user space in a data processing system. One embodiment provides a data processing system configured perform operations, comprising discovering a hardware device communicatively coupled to the communication bus, launching a user space driver daemon, establishing an inter-process communication (IPC) link between a first proxy interface for the user space driver daemon and a second proxy interface for a server process in a kernel space, receiving, at the first proxy interface, an access right to enable access to a memory buffer in the kernel space, and relaying an access request for the memory buffer from the user space driver daemon via a third-party proxy interface to enable the user space driver daemon to access the memory buffer, the access request based on the access right.

公开(公告)号：US20180349186A1

公开(公告)日：2018-12-06

申请号：US15870764

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol

IPC: G06F9/48 ,  G06F9/50

Abstract: Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US12147839B2

公开(公告)日：2024-11-19

申请号：US17392929

申请日：2021-08-03

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Bryan R. Hinch ,  Ronit Banerjee ,  Kushal Dalmia ,  Daniel A. Chimene ,  Jaidev P. Patwardhan

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/14

Abstract: Embodiments include an asymmetric multiprocessing (AMP) system having a first central processing unit (CPU) cluster comprising a first core type, and a second CPU cluster comprising a second core type, where the AMP system can update a thread metric for a first thread running on the first CPU cluster based at least on: a past shared resource overloaded metric of the first CPU cluster, and on-core metrics of the first thread. The on-core metrics can indicate that first thread contributes to contention of the same shared resource corresponding to the past shared resource overloaded metric of the first CPU cluster. The AMP system can assign the first thread to a different CPU cluster while other threads of the same thread group remain assigned to the first CPU cluster. The thread metric can include a Matrix Extension (MX) thread flag or a Bus Interface Unit (BIU) thread flag.

公开(公告)号：US11231966B2

公开(公告)日：2022-01-25

申请号：US16147077

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Bryan R. Hinch ,  Evan M. Hoke ,  Aditya Venkataraman

IPC: G06F9/50 ,  G06F9/48 ,  G06F1/3234 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/38 ,  G06F9/26 ,  G06F9/54 ,  G06F1/20 ,  G06F1/324 ,  G06F1/3206 ,  G06F9/30

Abstract: Systems and methods are disclosed for scheduling threads on an asymmetric multiprocessing system having multiple core types. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Metrics for workloads offloaded to co-processors can be tracked and integrated into metrics for the offloading thread group.

公开(公告)号：US10942850B2

公开(公告)日：2021-03-09

申请号：US16513225

申请日：2019-07-16

Applicant: Apple Inc.

Inventor： John G. Dorsey ,  Aditya Venkataraman ,  Bryan R. Hinch ,  Daniel A. Chimene ,  Andrei Dorofeev ,  Constantin Pistol

IPC: G06F12/00 ,  G06F12/0802

Abstract: A processing system can include a plurality of processing clusters. Each processing cluster can include a plurality of processor cores and a last level cache. Each processor core can include one or more dedicated caches and a plurality of counters. The plurality of counters may be configured to count different types of cache fills. The plurality of counters may be configured to count different types of cache fills, including at least one counter configured to count total cache fills and at least one counter configured to count off-cluster cache fills. Off-cluster cache fills can include at least one of cross-cluster cache fills and cache fills from system memory. The processing system can further include one or more controllers configured to control performance of one or more of the clusters, the processor cores, the fabric, and the memory responsive to cache fill metrics derived from the plurality of counters.