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    Memory Device Bandwidth Optimization
    11.
    发明申请
    Memory Device Bandwidth Optimization 有权

    公开(公告)号：US20230063772A1

    公开(公告)日：2023-03-02

    申请号：US17655324

    申请日：2022-03-17

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Shane J. Keil

    IPC: G06F13/16 ,  G06F1/06

    Abstract: Techniques for scheduling memory operations are disclosed in which alternate read/write commands within a multi-bank memory operation are delayed beyond a minimum timing parameter in order to increase memory data bus utilization. The remaining read/write commands are not delayed beyond the minimum timing parameter. Every other clock cycle (e.g., even clock cycles) within the memory operation is reserved for activate commands, while other commands such as sync and read/write are scheduled on the intervening clock cycles (e.g., odd clock cycles). For memory devices for which a sync command (which causes a clock of the memory data bus to start) is to precede a corresponding read/write command by a number of clock cycles that would place it in a cycle reserved for activate commands, a particular operation mode is disclosed in which the memory device internally delays a received sync command.

    Memory access scheduling using category arbitration
    12.
    发明授权
    Memory access scheduling using category arbitration 有权

    公开(公告)号：US10901617B2

    公开(公告)日：2021-01-26

    申请号：US16565386

    申请日：2019-09-09

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Shane J. Keil ,  Sukalpa Biswas ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijavaraj

    IPC: G06F12/00 ,  G06F3/06

    Abstract: A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

    ORDERING MEMORY REQUESTS BASED ON ACCESS EFFICIENCY
    16.
    发明申请
    ORDERING MEMORY REQUESTS BASED ON ACCESS EFFICIENCY 审中-公开

    公开(公告)号：US20200065028A1

    公开(公告)日：2020-02-27

    申请号：US16112624

    申请日：2018-08-24

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

    IPC: G06F3/06

    Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

    Read Arbiter Circuit with Dual Memory Rank Support
    17.
    发明申请
    Read Arbiter Circuit with Dual Memory Rank Support 有权

    公开(公告)号：US20250147901A1

    公开(公告)日：2025-05-08

    申请号：US19009464

    申请日：2025-01-03

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

    IPC: G06F13/16

    Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

    Memory error tracking and logging
    18.
    发明授权
    Memory error tracking and logging 有权

    公开(公告)号：US12253913B2

    公开(公告)日：2025-03-18

    申请号：US18438802

    申请日：2024-02-12

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Derek R. Kumar ,  Bernard J. Semeria ,  James Vash ,  Era K. Nangia ,  Gregory S. Mathews

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

    Memory request management system
    20.
    发明授权
    Memory request management system 有权

    公开(公告)号：US10783104B2

    公开(公告)日：2020-09-22

    申请号：US16595230

    申请日：2019-10-07

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Sukulpa Biswas

    IPC: G06F13/38 ,  G06F13/364 ,  G06F13/18 ,  G06F13/16

    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

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