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    Multi-Activation Techniques for Partial Write Operations
    1.
    发明申请
    Multi-Activation Techniques for Partial Write Operations 有权

    公开(公告)号：US20230068494A1

    公开(公告)日：2023-03-02

    申请号：US17410657

    申请日：2021-08-24

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

    IPC: G06F3/06

    Abstract: Techniques are disclosed relating to multi-activation techniques for wire operations with multiple partial writes. In some embodiments, a memory controller is configured to access data in a memory device that supports partial writes having a first size using read-modify-write operations and non-partial writes having a second size that is greater than the first size. In some embodiments, the memory controller is configured to queue a first write operation having the second size, where the first write operation includes multiple partial writes. In some embodiments, the memory controller is configured to send separate activate signals to the memory device to activate a bank of the memory device to perform different proper subsets of the multiple partial writes. This may allow interleaving of other accesses to a memory bank and merging of writes while waiting for a current activation, in some embodiments.

    Read Arbiter Circuit with Dual Memory Rank Support
    4.
    发明申请
    Read Arbiter Circuit with Dual Memory Rank Support 有权

    公开(公告)号：US20250147901A1

    公开(公告)日：2025-05-08

    申请号：US19009464

    申请日：2025-01-03

    Applicant: Apple Inc.

    Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala

    IPC: G06F13/16

    Abstract: A memory control circuit coupled to multiple memory ranks may receive read and write requests for a different ranks of the multiple memory ranks. The memory control may allocate write requests to different slots based on the write requests target memory rank, and may adjust the number of slots available for a given memory rank during a write turn to improve write efficiency. The memory control circuit may also determine a number of ranks switches within a read turn based on whether a particular quality-of-service requirement associated with the read requests is being satisfied.

    Memory request management system
    5.
    发明授权
    Memory request management system 有权

    公开(公告)号：US10783104B2

    公开(公告)日：2020-09-22

    申请号：US16595230

    申请日：2019-10-07

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Sukulpa Biswas

    IPC: G06F13/38 ,  G06F13/364 ,  G06F13/18 ,  G06F13/16

    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

    MEMORY ACCESS SCHEDULING USING CATEGORY ARBITRATION
    6.
    发明申请
    MEMORY ACCESS SCHEDULING USING CATEGORY ARBITRATION 审中-公开

    公开(公告)号：US20200081622A1

    公开(公告)日：2020-03-12

    申请号：US16565386

    申请日：2019-09-09

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Shane J. Keil ,  Sukalpa Biswas ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijavaraj

    IPC: G06F3/06

    Abstract: A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

    Memory request management system
    7.
    发明授权
    Memory request management system 有权

    公开(公告)号：US10437758B1

    公开(公告)日：2019-10-08

    申请号：US16024658

    申请日：2018-06-29

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Sukulpa Biswas

    IPC: G06F13/38 ,  G06F13/364 ,  G06F13/18 ,  G06F13/16

    Abstract: A memory request management system may include a memory device and a memory controller. The memory controller may include a read queue, a write queue, an arbitration circuit, a read credit allocation circuit, and a write credit allocation circuit. The read queue and write queue may store corresponding requests from request streams. The arbitration circuit may send requests from the read queue and write queue to the memory device based on locations of addresses indicated by the requests. The read credit allocation circuit may send an indication of an available read credit to a request stream in response to a read request from the request stream being sent from the read queue to the memory device. The write credit allocation circuit may send an indication of an available write credit to a request stream in response to a write request from the request stream being stored at the write queue.

    Memory Bank Hotspotting
    9.
    发明申请
    Memory Bank Hotspotting 有权

    公开(公告)号：US20220357879A1

    公开(公告)日：2022-11-10

    申请号：US17313811

    申请日：2021-05-06

    Applicant: Apple Inc.

    Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

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