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公开(公告)号：US09397567B2
公开(公告)日：2016-07-19
申请号：US14287931
申请日：2014-05-27
Applicant: Apple Inc.
Inventor： Shawn Searles , Emerson S Fang
CPC classification number: H02M3/158 , H02M1/088 , H02M3/1584 , H02M3/1588 , Y02B70/1466
Abstract: A method and apparatus for augmenting an external voltage regulator with a shunt integrated voltage regulator is disclosed. In one embodiment, an integrated circuit (IC) includes a load circuit coupled to a supply voltage node. The supply voltage node is electrically coupled to receive a supply voltage from an external voltage regulator. The IC also includes a shunt integrated voltage regulator coupled to the supply voltage node and implemented on the same IC die as the load circuit. If the supply voltage falls below a specified value (e.g., to increased current demand), the integrated voltage regulator may begin supplying current to the load. This may cause the supply voltage to return to within its specified range of the specified value, while allowing the external voltage regulator sufficient time to respond to the increased current demand. Thus, voltage droops on the supply voltage node may be minimized.
Abstract translation: 公开了一种用于利用分流集成稳压器增强外部电压调节器的方法和装置。 在一个实施例中，集成电路（IC）包括耦合到电源电压节点的负载电路。 电源节点电耦合以从外部电压调节器接收电源电压。 IC还包括耦合到电源电压节点并在与负载电路相同的IC管芯上实现的分流集成稳压器。 如果电源电压低于指定值（例如，增加电流需求），集成稳压器可能开始向负载提供电流。 这可能导致电源电压恢复到指定值的指定范围内，同时允许外部电压调节器有足够的时间来响应增加的电流需求。 因此，电源电压节点上的电压下降可以被最小化。
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12.发明申请公开(公告)号：US20250167048A1
公开(公告)日：2025-05-22
申请号：US19028523
申请日：2025-01-17
Applicant: Apple Inc.
Inventor： Vidhya Ramachandran , Jun Zhai , Chonghua Zhong , Kunzhong Hu , Shawn Searles , Joseph T. DiBene, II , Mengzhi Pang
Abstract: A disclosed system includes a package body that includes a system-on-a-chip (SoC) and an interconnect region. In an embodiment, the interconnect region includes a first conductive path between the SoC and a voltage regulator module (VRM), a second conductive path between the SoC and a first external connection, and a third conductive path between the VRM and a second external connection. In another embodiment, the VRM is positioned between and coupled to a first portion of the SoC and a first surface of the interconnect region. A second portion of the SoC is coupled directly to the first surface of the interconnection region. In another embodiment, the interconnect region has first and second opposing surfaces. The SoC is positioned on the first surface of the interconnect region. The VRM is externally coupled to a first surface of the package body adjacent to the second surface of the interconnect region.
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公开(公告)号：US20240396452A1
公开(公告)日：2024-11-28
申请号：US18792905
申请日：2024-08-02
Applicant: Apple Inc.
Inventor： Jay B. Fletcher , Nathan F. Hanagami , Sanjay Pant , Hao Zhou , Shawn Searles
Abstract: A voltage regulator circuit included in a computer system may employ a control circuit and a switch array that includes multiple switch circuits. Different groups of switch circuits that include respective groups of switch devices are coupled between an input power supply node and corresponding regulated power supply nodes. To maintain desired respective voltages on the regulated power supply nodes, the control circuit compares the voltages of the regulated power supply nodes to corresponding reference voltages and, based on results of the comparisons, opens and closes various ones of the switch devices included in the different groups of switch circuits.
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公开(公告)号：US12068324B2
公开(公告)日：2024-08-20
申请号：US17358790
申请日：2021-06-25
Applicant: Apple Inc.
Inventor： Jared L. Zerbe , Emerson S. Fang , Jun Zhai , Shawn Searles
IPC: H01L27/10 , H01G4/228 , H01L23/00 , H01L23/13 , H01L23/48 , H01L23/498 , H01L23/64 , H01L25/065 , H01L25/16 , H01L25/18 , H01L49/02 , H01L23/50 , H01L25/10
CPC classification number: H01L27/101 , H01G4/228 , H01L23/13 , H01L23/481 , H01L23/49816 , H01L23/642 , H01L24/14 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L28/40 , H01L23/49827 , H01L23/50 , H01L24/16 , H01L24/48 , H01L25/105 , H01L2224/0401 , H01L2224/13025 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16227 , H01L2224/16265 , H01L2224/32225 , H01L2224/45099 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00012 , H01L2924/00014 , H01L2924/1033 , H01L2924/12042 , H01L2924/1205 , H01L2924/1427 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15153 , H01L2924/15159 , H01L2924/15174 , H01L2924/15311 , H01L2924/15331 , H01L2924/157 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19103 , H01L2924/19104 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2924/00014 , H01L2224/45099 , H01L2924/00014 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.
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公开(公告)号：US20240241571A1
公开(公告)日：2024-07-18
申请号：US18622502
申请日：2024-03-29
Applicant: Apple Inc.
Inventor： Shawn Searles , Sanjay Pant , Ludmil N. Nikolov , Tiago Filipe Galhoz Patrao , Enrico Zanetti , Hao Zhou , Vincenzo Bisogno
IPC: G06F1/3296 , H02M1/00 , H02M3/157
CPC classification number: G06F1/3296 , H02M1/0006 , H02M1/0025 , H02M1/007 , H02M3/157
Abstract: A power delivery system included in a computer system uses multiple power converter circuits to generate respective voltage levels on multiple power supply nodes. An embodiment of the power delivery system includes an input power converter circuit that generates a voltage level for use by host and follower power converter circuits. The host power converter circuit generates an external demand current that is shared by multiple follower power converter circuits to regulate the voltage level on the multiple power supply nodes. The power delivery system can be scaled to different platforms of the computer system by adjusting the number of follower power converter circuits.
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Patent Agency Ranking
公开(公告)号：US11983063B2
公开(公告)日：2024-05-14
申请号：US17823949
申请日：2022-08-31
Applicant: Apple Inc.
Inventor： Shawn Searles , Sanjay Pant , Ludmil N. Nikolov , Tiago Filipe Galhoz Patrao , Enrico Zanetti , Hao Zhou , Vincenzo Bisogno
IPC: G06F1/32 , G06F1/3296 , H02M1/00 , H02M3/157
CPC classification number: G06F1/3296 , H02M1/0006 , H02M1/0025 , H02M1/007 , H02M3/157
Abstract: A power delivery system included in a computer system using multiple power converter circuits to generate respective voltage levels on multiple power supply nodes. The power delivery system includes a step-down power converter circuit that generates a voltage level for use by host and follower power converter circuits. The host power converter circuit generates an external demand current that is shared by multiple follower power converter circuits to regulate the voltage level on the multiple power supply nodes. The power delivery system can be scaled to different platforms of the computer system by adjusting the number of follower power converter circuits.
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公开(公告)号：US20240126353A1
公开(公告)日：2024-04-18
申请号：US18497443
申请日：2023-10-30
Applicant: Apple Inc.
Inventor： Shawn Searles , Fabio Gozzini , Sanjay Pant , Inder M. Sodhi
CPC classification number: G06F1/26 , G01R15/146 , G11C7/1096
Abstract: A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.
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公开(公告)号：US11722060B2
公开(公告)日：2023-08-08
申请号：US16936410
申请日：2020-07-22
Applicant: Apple Inc.
Inventor： Victor Zyuban , Norman J. Rohrer , Shawn Searles
Abstract: A converter circuit, included in a power converter circuit, may generate a given voltage level on a regulated power supply node of a computer system. A control circuit may monitor a voltage level and assert a control signal in response to a determination that a regulation event has occurred. A boost converter circuit, included in the power converter circuit, may inject charge into to the regulated power supply node via a capacitor, in response to an assertion of the control signal.
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公开(公告)号：US11669145B2
公开(公告)日：2023-06-06
申请号：US17476186
申请日：2021-09-15
Applicant: Apple Inc.
Inventor： Shawn Searles , Preethi Damodaran , Ofir Gilad , Michele De Fazio , Inder M. Sodhi , Enrico Zanetti , Olivier Girard , Lothar Münch , Andrea Barsanti , Andrea Lazzeri
IPC: G06F1/32 , G06F1/324 , G06F1/3296 , G06F1/3234
CPC classification number: G06F1/324 , G06F1/3296 , G06F1/3275
Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.
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公开(公告)号：US20220300022A1
公开(公告)日：2022-09-22
申请号：US17658408
申请日：2022-04-07
Applicant: Apple Inc.
Inventor： Shawn Searles , Victor Zyuban , Mohamed Abu-Rahma
Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.
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