公开(公告)号：US20250167048A1

公开(公告)日：2025-05-22

申请号：US19028523

申请日：2025-01-17

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

Abstract: A disclosed system includes a package body that includes a system-on-a-chip (SoC) and an interconnect region. In an embodiment, the interconnect region includes a first conductive path between the SoC and a voltage regulator module (VRM), a second conductive path between the SoC and a first external connection, and a third conductive path between the VRM and a second external connection. In another embodiment, the VRM is positioned between and coupled to a first portion of the SoC and a first surface of the interconnect region. A second portion of the SoC is coupled directly to the first surface of the interconnection region. In another embodiment, the interconnect region has first and second opposing surfaces. The SoC is positioned on the first surface of the interconnect region. The VRM is externally coupled to a first surface of the package body adjacent to the second surface of the interconnect region.

公开(公告)号：US20250158519A1

公开(公告)日：2025-05-15

申请号：US19021045

申请日：2025-01-14

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L23/00 ,  H01L23/522 ,  H10D1/00

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US20220013504A1

公开(公告)日：2022-01-13

申请号：US17484188

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US11101732B2

公开(公告)日：2021-08-24

申请号：US16943139

申请日：2020-07-30

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US10818632B1

公开(公告)日：2020-10-27

申请号：US15943673

申请日：2018-04-02

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/77

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US10103138B2

公开(公告)日：2018-10-16

申请号：US15658670

申请日：2017-07-25

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/08 ,  H01L27/06 ,  H01L21/77 ,  H01L49/02 ,  H01L23/64 ,  H01L23/00 ,  H01L25/16

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

公开(公告)号：US20170018546A1

公开(公告)日：2017-01-19

申请号：US15057588

申请日：2016-03-01

Applicant: Apple Inc.

Inventor： Jun Zhai ,  Vidhya Ramachandran ,  Kunzhong Hu ,  Mengzhi Pang ,  Chonghua Zhong

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/77

CPC classification number: H01L27/0641 ,  H01L21/77 ,  H01L23/642 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L28/10 ,  H01L28/40 ,  H01L28/90 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24195 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105

Abstract: In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device.

Abstract translation: 在一些实施例中，系统可以包括集成电路。 集成电路可以包括包括第一表面，基本上与第一表面相对的第二表面的衬底和耦合到第一表面的第一组电导体。 第一组电导体可以用于将集成电路电连接到电路板。 集成电路可以包括使用第二组电导体耦合到衬底的第二表面的半导体管芯。 集成电路可以包括被定义为与集成电路集成的无源器件。 无源器件可以位于第二表面和第一组电导体中的至少一个之间。 芯片可以电连接到无源器件的第二侧。 无源器件的第一侧可用于电连接到第二器件。

公开(公告)号：US20230040308A1

公开(公告)日：2023-02-09

申请号：US17397834

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US11158607B2

公开(公告)日：2021-10-26

申请号：US16503806

申请日：2019-07-05

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kwan-Yu Lai ,  Kunzhong Hu ,  Vidhya Ramachandran

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L23/60 ,  H01L23/00 ,  H01L25/00

Abstract: Stitched die packaging techniques and structures are described in which reconstituted chips are formed using wafer reconstitution and die-stitching techniques. In an embodiment, a chip includes a reconstituted chip-level back end of the line (BEOL) build-up structure to connect a die set embedded in an inorganic gap fill material.

公开(公告)号：US20200176427A1

公开(公告)日：2020-06-04

申请号：US16205679

申请日：2018-11-30

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Chonghua Zhong ,  Jun Zhai ,  Long Huang ,  Mengzhi Pang ,  Rohan U. Mandrekar

IPC: H01L25/16 ,  H01L21/66 ,  G01R31/02

Abstract: Integrated passive devices (IPDs), electronic packaging structures, and methods of testing IPDs are described. In an embodiment, an electronic package structure includes an IPD with an array of capacitor banks that are electrically separate in the IPD, and a package routing that includes an interconnect electrically connected to an IC and a plurality of the capacitor banks in parallel.