METHODS AND APPARATUSES FOR PACKAGING AN ULTRASOUND-ON-A-CHIP

    公开(公告)号:WO2019152340A1

    公开(公告)日:2019-08-08

    申请号:PCT/US2019/015518

    申请日:2019-01-29

    Abstract: Aspects of the disclosure described herein related to packaging an ultrasound-on-a- chip. In some embodiments, an apparatus includes an ultrasound-on-a-chip that has through- silicon vias (TSVs) and an interposer coupled to the ultrasound-on-a-chip and including vias, where the ultrasound-on-a-chip is coupled to the interposer such that the TSVs in the ultrasound-on-a-chip are electrically connected to the vias in the interposer. In some embodiments, an apparatus includes an ultrasound-on-a-chip having bond pads, an interposer that has bond pads and that is coupled to the ultrasound-on-a-chip, and wirebonds extending from the bond pads on the ultrasound-on-a-chip to the bond pads on the interposer.

    ADAPTIVE CAVITY THICKNESS CONTROL FOR MICROMACHINED ULTRASONIC TRANSDUCER DEVICES

    公开(公告)号:WO2020176149A1

    公开(公告)日:2020-09-03

    申请号:PCT/US2019/061419

    申请日:2019-11-14

    Abstract: A method of forming an ultrasonic transducer device includes forming and patterning a film stack over a substrate, the film stack comprising a metal electrode layer and a chemical mechanical polishing (CMP) stop layer formed over the metal electrode layer; forming an insulation layer over the patterned film stack; planarizing the insulation layer to the CMP stop layer; measuring a remaining thickness of the CMP stop layer; and forming a membrane support layer over the patterned film stack, wherein the membrane support layer is formed at thickness dependent upon the measured remaining thickness of the CMP stop layer, such that a combined thickness of the CMP stop layer and the membrane support layer corresponds to a desired transducer cavity depth.

    VERTICAL PACKAGING FOR ULTRASOUND-ON-A-CHIP AND RELATED METHODS

    公开(公告)号:WO2019213448A1

    公开(公告)日:2019-11-07

    申请号:PCT/US2019/030480

    申请日:2019-05-02

    Abstract: Vertical packaging configurations for ultrasound chips are described. Vertical packaging may involve use of integrated interconnects other than wires for wire bonding. Examples of such integrated interconnects include edge-contact vias, through silicon vias and conductive pillars. Edge-contact vias are vias defined in a trench formed in the ultrasound chip. Multiple vias may be provided for each trench, thus increasing the density of vias. Such vias enable electric access to the ultrasound transducers. Through silicon vias are formed through the silicon handle and provide access from the bottom surface of the ultrasound chip. Conductive pillars, including copper pillars, are disposed around the perimeter of an ultrasound chip and provide access to the ultrasound transducers from the top surface of the chip. Use of these types of packaging techniques can enable a substantial reduction in the dimensions of an ultrasound device.

    PRESSURE PORT FOR ULTRASONIC TRANSDUCER ON CMOS SENSOR

    公开(公告)号:WO2019213388A1

    公开(公告)日:2019-11-07

    申请号:PCT/US2019/030388

    申请日:2019-05-02

    Abstract: Micromachined ultrasonic transducers having pressure ports are described. The micromachined ultrasonic transducers may comprise flexible membranes configured to vibrate over a cavity. The cavity may be sealed, in some instances by the membrane itself. A pressure port may provide access to the cavity, and thus control of the cavity pressure. In some embodiments, an ultrasound device including an array of micromachined ultrasonic transducers is provided, with pressure ports for at least some of the ultrasonic transducers. The pressure ports may be used to control pressure across the array.

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